DF2168VTE33 Renesas Electronics America, DF2168VTE33 Datasheet - Page 501

MCU FLASH 3V 256K 33MHZ 144TQFP

DF2168VTE33

Manufacturer Part Number
DF2168VTE33
Description
MCU FLASH 3V 256K 33MHZ 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2168VTE33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2168VTE33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.3.8
ICXR enables or disables the I
operation, and indicates the status of receive/transmit operations.
Bit
7
6
Bit Name
STOPIM
HNDS
I
2
C Bus Extended Control Register (ICXR)
0
Initial
Value
0
2
C bus interface interrupt generation and continuous receive
R/W
R/W
R/W
Stop Condition Interrupt Source Mask
Description
Enables or disables the interrupt generation when the stop
condition is detected in slave mode.
0: Enables IRIC flag setting and interrupt generation when
1: Disables IRIC flag setting and interrupt generation when
Handshake Receive Operation Select
Enables or disables continuous receive operation in
receive mode.
0: Enables continuous receive operation
1: Disables continuous receive operation
When the HNDS bit is cleared to 0, receive operation is
performed continuously after data has been received
successfully while ICDRF flag is 0.
When the HNDS bit is set to 1, SCL is fixed to the low
level after data has been received successfully while
ICDRF flag is 0; thus disabling the next data to be
transferred. The bus line is released and next receive
operation is enabled by reading the receive data in ICDR.
the stop condition is detected (STOP = 1 or ESTP = 1)
in slave mode.
the stop condition is detected.
Rev. 3.00, 03/04, page 459 of 830

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