DF2168VTE33 Renesas Electronics America, DF2168VTE33 Datasheet - Page 575
![MCU FLASH 3V 256K 33MHZ 144TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2168VTE33
Manufacturer Part Number
DF2168VTE33
Description
MCU FLASH 3V 256K 33MHZ 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2168VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2168VTE33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 575 of 876
- Download datasheet (5Mb)
Bit
4
3
2
1
SWMF
C/D3
DBU32
IBF3A
Bit Name Initial Value Slave Host Description
0
0
0
0
R/(W)* R
R
R/W
R
R/W
R
R
R
Slave Write Mode Flag
Indicates that slave write mode is entered by writing
to TWR0 from the slave processor (this LSI). In the
event of simultaneous writes by the master and the
slave, the master write has priority.
0: [Clearing condition]
1: [Setting condition]
Command/Data
When the host processor writes to an IDR3 register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR3 contains data or a command.
0: Content of input data register (IDR3) is data
1: Content of input data register (IDR3) is a
Defined by User
The user can use this bit as necessary.
Input Data Register Full
Indicates whether or not there is receive data in
IDR3. This is an internal interrupt source to the slave
processor (this LSI).
0: There is not receive data in IDR3
[Clearing condition]
When the slave processor reads IDR3
1: There is receive data in IDR3
[Setting condition]
When the host processor writes to IDR3 using I/O
write cycle
When the host processor reads TWR15 using I/O
read cycle, or the slave processor writes 0 to the
SWMF bit
command
When the slave processor writes to TWR0 while
MWMF = 0
Rev. 3.00, 03/04, page 533 of 830
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