DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 589

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 16.6 I
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
Note:
SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
Electrical Characteristics, and as shown in table 26.10. Note that the I
timing specifications will not be met with a system clock frequency of less than 5 MHz.
The I
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table
below.
* 6t
2
C bus interface specification for the SCL rise time t
cyc
2
C Bus Timing (SCL and SDA Output)
when IICX is 0, 12t
cyc
when 1.
2
C bus interface monitors the SCL line and synchronizes
Symbol
t
t
t
t
t
t
t
t
t
SCLO
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDAHO
sr
(the time for SCL to go from low to V
cyc
2
C bus interface, the high period of SCL is
, as shown in I
Output Timing
28t
0.5t
0.5t
0.5t
0.5t
1t
0.5t
1t
1t
3t
SCLO
SCLLO
SCLL
cyc
Rev. 4.00 Sep 27, 2006 page 543 of 1130
cyc
SCLO
SCLO
SCLO
SCLO
SCLO
–(6t
to 256t
–3t
–1t
–1t
+2t
sr
Section 16 I
cyc
cyc
is under 1000 ns (300 ns for high-
cyc
cyc
cyc
or 12t
2
cyc
C Bus Timing in section 26,
cyc
* )
2
C bus interface AC
2
C Bus Interface [Option]
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
REJ09B0327-0400
Notes
Figure 26.28
(reference)
IH
) exceeds