M37632EFFP#U2 Renesas Electronics America, M37632EFFP#U2 Datasheet - Page 43

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M37632EFFP#U2

Manufacturer Part Number
M37632EFFP#U2
Description
IC 740 MCU 80QFP
Manufacturer
Renesas Electronics America
Datasheet

Specifications of M37632EFFP#U2

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
B B S
Accumulator bit
Relative
Zero page bit
Relative
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Status flag :
Notes 1: rr
Addressing mode
Operation :
Function :
2: When a branch is executed, add 2 to the cycle number.
3: When executing the BBS instruction after the contents of the interrupt
request bit is changed, one instruction or more must be passed
before the BBS instruction is executed.
16
=$hhll–( +n). The rr
When (Mi) or (Ai) = 1, (PC) ← (PC) + n + REL
This instruction tests the designated bit i of the M or A and
takes a branch if the bit is 1. The branch address is specified
by a relative address. If the bit is 0, next instruction is exe-
cuted.
No change
∆BBS∆i,A,$hhll
∆BBS∆i,$zz,$hhll
page 35 of 185
(Mi) or (Ai) = 0, (PC) ← (PC) + n
Statement
n : If addressing mode is Zero Page Bit Relative, n=3. And if
B
addressing mode is Accumulator Bit Relative, n=2.
RANCH ON
16
is a value in a range of –128 to +127.
(20i+3)
(20i+7)
zz
Machine codes
16
B
, rr
IT
16
16
16
S
, rr
,
ET
16
Byte number
2
3
B B S
Cycle number
4
5

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