UPD78F9222MC-5A4-A Renesas Electronics America, UPD78F9222MC-5A4-A Datasheet - Page 391

• Manufacturer Part Number: UPD78F9222MC-5A4-A
• Description: MCU 8BIT 4KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9222MC-5A4-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-bit timer/
event
counter
00
Function
CRC00:
Capture/
compare
control register
00
TOC00: 16-bit
timer output
control register
00
PRM00:
Prescaler mode
register 00
Details of
Function
When the clear & start mode entered on a match between TM00 and CR000 is
selected by 16-bit timer mode control register 00 (TMC00), CR000 should not
be specified as a capture register.
To ensure the reliability of the capture operation, the capture trigger requires a
pulse longer than two cycles of the count clock selected by prescaler mode
register 00 (PRM00) (refer to Figure 6-17).
The timer operation must be stopped before setting other than OSPT00.
If LVS00 and LVR00 are read, 0 is read.
OSPT00 is automatically cleared after data is set, so 0 is read.
Do not set OSPT00 to 1 other than in one-shot pulse output mode.
A write interval of two cycles or more of the count clock selected by prescaler
mode register 00 (PRM00) is required, when OSPT00 is set to 1 successively.
When TOE00 is 0, set TOE00, LVS00, and LVR00 at the same time with the 8-
bit memory manipulation instruction. When TOE00 is 1, LVS00 and LVR00 can
be set with the 1-bit memory manipulation instruction.
Always set data to PRM00 after stopping the timer operation.
If the valid edge of the TI000 pin is to be set as the count clock, do not set the
clear/start mode and the capture trigger at the valid edge of the TI000 pin.
In the following cases, note with caution that the valid edge of the TI0n0 pin is
detected.
<1> Immediately after a system reset, if a high level is input to the TI0n0 pin,
the operation of the 16-bit timer counter 00 (TM00) is enabled
<2> If the TM00 operation is stopped while the TI0n0 pin is high level, TM00
operation is then enabled after a low level is input to the TI0n0 pin
<3> If the TM00 operation is stopped while the TI0n0 pin is low level, TM00
operation is then enabled after a high level is input to the TI0n0 pin
The sampling clock used to eliminate noise differs when a TI000 valid edge is
used as the count clock and when it is used as a capture trigger. In the former
case, the count clock is f
prescaler mode register 00 (PRM00). The capture operation is not performed
until the valid edge is sampled and the valid level is detected twice, thus
eliminating noise with a short pulse width.
When using P31 as the input pin (TI010) of the valid edge, it cannot be used as
a timer output pin (TO00). When using P31 as the timer output pin (TO00), it
cannot be used as the input pin (TI010) of the valid edge.
If the rising edge or both rising and falling edges are specified as the valid
edge of the TI0n0 pin, a rising edge is detected immediately after the TM00
operation is enabled.
If the falling edge or both rising and falling edges are specified as the valid
edge of the TI0n0 pin, a falling edge is detected immediately after the TM00
operation is enabled.
If the rising edge or both rising and falling edges are specified as the valid
edge of the TI0n0 pin, a rising edge is detected immediately after the TM00
operation is enabled.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16898EJ6V0UD
XP
, and in the latter case the count clock is selected by
Cautions
pp. 94,
121
pp. 94,
124
pp. 95,
122
pp. 95,
122
pp. 95,
122
pp. 95,
122
pp. 95,
122
p. 95
pp. 97,
122
pp. 97,
124
pp. 97,
126
pp. 97,
126
pp. 97,
126
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