UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 126

• Manufacturer Part Number: UPD78F0513AGB-GAF-AX
• Description: MCU 8BIT 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGB-GAF-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
(3) Stack pointer (SP)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(d) Auxiliary carry flag (AC)
(e) In-service priority flag (ISP)
(f) Carry flag (CY)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area
can be set as the stack area.
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the
stack memory.
Each stack operation saves/restores data as shown in Figures 3-23 and 3-24.
Caution Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.
This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-level
vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H) (see
20.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be acknowledged. Actual
request acknowledgment is controlled by the interrupt enable flag (IE).
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon
rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
using the stack.
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
15
Figure 3-22. Format of Stack Pointer
CHAPTER 3 CPU ARCHITECTURE
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