MAXQ7670ATL+T Maxim Integrated Products, MAXQ7670ATL+T Datasheet - Page 15

• Manufacturer Part Number: MAXQ7670ATL+T
• Description: IC MCU W/10BIT ADC 40TQFN-EP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ7670ATL+T

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-TQFN Exposed Pad
• Processor Series: MAXQ7670
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, JTAG, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIN
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
40
—
ADCCNV
REGEN2
RESET
NAME
DGND
DVDD
AVDD
XOUT
SCLK
MOSI
MISO
P0.4/
TDO
TMS
TCK
P0.5
XIN
TDI
EP
______________________________________________________________________________________
SPI Serial Clock. SCLK is the SPI interface serial clock I/O. In SPI master mode, SCLK is an output. While in
SPI slave mode, SCLK is an input.
SPI Serial Data I/O. MOSI is the SPI interface serial data output in master mode or serial data input in slave
mode.
SPI Serial Data I/O. MISO is the SPI interface serial data input in master mode or serial data output in slave
mode.
Active-Low +2.5V Linear Regulator Enable Input. Connect REGEN2 to GNDIO to enable the +2.5V linear
regulator. Connect to DVDDIO to disable the +2.5V linear regulator.
JTAG Serial Test Data Output. TDO is the JTAG serial test, data output.
JTAG Test Mode Select. TMS is the JTAG test mode, select input.
JTAG Serial Test Data Input. TDI is the JTAG serial test, data input.
JTAG Serial Test Clock Input. TCK is the JTAG serial test, clock input.
Port 0 Bit 4/ADC Start Conversion Control. P0.4 is a general-purpose digital I/O with interrupt/wake-up
capability. ADCCNV is a firmware-configurable, rising or falling edge, start/convert signal used to trigger
ADC conversions. The alternative function, ADCCNV, is selected using the register bits ACNT[2:0]. When
using ADCCNV as a trigger for ADC conversion, set P0.4/ADCCNV as an input using the PD0 register. This
action prevents any unintentional interference in the SARADC operation.
Port 0 Bit 5. P0.5 is a general-purpose digital I/O with interrupt/wake-up capability.
Reset Input/Output. Active-low input/output with internal 55kΩ pullup to DVDDIO. Drive low to reset the
MAXQ7670. The MAXQ20 µC core holds RESET low during POR and during DVDD brownout conditions.
Digital Ground
High-Frequency Crystal Output. Connect an external crystal to XIN and XOUT for normal operation, or leave
unconnected if XIN is driven with an external clock source. Leave unconnected if an external clock source
is not used.
H i g h- Fr eq uency C r ystal Inp ut. C onnect an exter nal cr ystal or r esonator to X IN and X OU T for nor m al op er ati on,
or d r i ve X IN w i th an exter nal cl ock sour ce. Leave unconnected i f an exter nal cl ock sour ce i s not used .
D i g i tal S up p l y V ol tag e. D V D D sup p l i es i nter nal d i g i tal cor e and fl ash m em or y. D V D D i s d i r ectl y connected to
the outp ut of the i nter nal + 2.5V l i near r eg ul ator . D i sab l e the i nter nal r eg ul ator ( thr oug h REG EN 2) to connect an
exter nal sup p l y. Byp ass D V D D to D GN D w i th a 0.1µF cap aci tor as cl ose as p ossi b l e to the d evi ce.
Analog Supply Voltage. AVDD supplies PGA and ADC. AVDD is directly connected to the output of the
internal +3.3V linear regulator. Disable the internal regulator (via software) to connect an external supply.
Bypass AVDD to AGND with a 0.1µF capacitor as close as possible to the device.
Exposed Pad. Connect EP to the ground plane.
PGA, 64KB Flash, and CAN Interface
Microcontroller with 10-Bit ADC,
FUNCTION
Pin Description (continued)
15