MAXQ7670ATL+T Maxim Integrated Products, MAXQ7670ATL+T Datasheet - Page 29

• Manufacturer Part Number: MAXQ7670ATL+T
• Description: IC MCU W/10BIT ADC 40TQFN-EP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ7670ATL+T

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-TQFN Exposed Pad
• Processor Series: MAXQ7670
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, JTAG, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Advanced power-management features minimize
power consumption by dynamically matching the pro-
cessing speed of the device to the required perfor-
mance level. During periods of reduced activity, lower
the system clock speed to reduce power consumption.
Use the source-clock-divide feature to reduce the sys-
tem clock speed to 1/2, 1/4, and 1/8 of the source
clock’s speed. A lower power state is thus achievable
without additional hardware. For extremely power-sen-
sitive applications, two additional low-power modes are
available:
• PMM: divide-by-256 power-management mode
• Stop mode (STOP = 1)
Enabling PMM reduces the system clock speed to
1/256 of the source clock speed, and significantly
reduces power consumption. The optional switchback
feature allows enabled interrupt sources including
external, CAN, and SPI interrupts to bring the µC out of
the power-management mode and to run at a faster
system clock speed.
Power consumption is minimal in stop mode. In this
mode, the external oscillator, internal RC oscillator, sys-
tem clock, and all processing activity stop. Triggering
an enabled external interrupt or applying an external
reset signal to RESET brings the µC out of stop mode.
Upon exiting stop mode, the µC can either wait for the
external crystal to warm up, or execute immediately by
using the internal RC oscillator as the crystal warms up.
Multiple interrupt sources are available for quick
response to internal and external events. Examples of
events that can trigger an interrupt are:
• Watchdog interrupt
• GPIO0–GPIO7 interrupts
• SPI mode fault, write collision, receive overrun, and
• Timer 0 low compare, low overflow, capture/compare,
• CAN0 receive and transmit interrupts and a change in
• ADC data ready interrupt
• Voltage brownout interrupts
• Crystal oscillator failure interrupt
(PMME = 1)
transfer complete interrupts
and overflow interrupts
CAN0 status register interrupt
______________________________________________________________________________________
Power Management
PGA, 64KB Flash, and CAN Interface
Microcontroller with 10-Bit ADC,
Interrupts
Each interrupt has flag and enable bits. The flag indi-
cates whether an interrupt event has occurred. Enable
the µC to generate an interrupt by setting the enable
bit. Interrupts are organized into modules. Enable the
interrupt individually, by module, and globally.
The µC jumps to an ISR after an enabled interrupt event
occurs. Use the interrupt identification register (IIR) to
determine whether the interrupt is a system or peripher-
al interrupt. In the ISR, clear the interrupt flag to elimi-
nate repeated interrupts from the same event. After
clearing the interrupt, allow a delay before issuing the
return from interrupt (RETI) instruction. Asynchronous
interrupt flags require a one-instruction delay and syn-
chronous interrupt flags require a two-instruction delay.
The MAXQ architecture uses a single interrupt vector
(IV) and single ISR design. The IV register holds the
address of the ISR. In the application code, assign a
unique address to each ISR. Otherwise, the IV automat-
ically jumps to 0000h, the beginning of application
code, after an enabled interrupt occurs.
Reset sources are provided for µC control. Although
code execution stops in the reset state, the internal RC
oscillator continues to oscillate. Internal resets, such as
the power-on and watchdog resets, pull RESET low.
An internal POR circuit enhances system reliability. The
POR circuit forces the device to perform a POR when-
ever a rising voltage on DVDD climbs above the POR
threshold. At this point the following events occur:
• All registers and circuits enter the default state
• The POR flag (WDCN.7) sets to indicate if the source
• The internal 15MHz RC oscillator becomes the clock
• Code execution begins at location 8000h
Refer to the MAXQ7670 User’s Guide for more information.
The watchdog timer functions are described in the
MAXQ7670 User’s Guide . Execution resumes at loca-
tion 8000h following a watchdog timer reset.
Pulling RESET low externally causes the device to enter
the reset state. The external reset functions as
described in the MAXQ7670 User’s Guide . Execution
resumes at location 8000h after RESET is released.
of the reset was a loss of power
source
External System Reset
Watchdog Timer Reset
Power-On Reset (POR)
Reset Sources
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