SAF-C165-LF 3V HA Infineon Technologies, SAF-C165-LF 3V HA Datasheet - Page 64
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SAF-C165-LF 3V HA
Manufacturer Part Number
SAF-C165-LF 3V HA
Description
IC MCU 16BIT ROM/LESS TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C165-LF_HA.pdf
(77 pages)
Specifications of SAF-C165-LF 3V HA
Core Processor
C166
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
77
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
1xASC, 1xSSC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
77
Number Of Timers
5
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Packages
PG-TQFP-100
Max Clock Frequency
20.0 MHz
Sram (incl. Cache)
2.0 KByte
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
F165LF3VHAXT
SAF-C165-LF3VHA
SAF-C165-LF3VHAINTR
SAF-C165-LF3VHATR
SAF-C165-LF3VHATR
SAFC165LF3VHAXT
SP000011632
SAF-C165-LF3VHA
SAF-C165-LF3VHAINTR
SAF-C165-LF3VHATR
SAF-C165-LF3VHATR
SAFC165LF3VHAXT
SP000011632
Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
Parameter
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
1)
2)
3)
Data Sheet
RW-delay and t
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
1)
A
1)
refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
Symbol
t
t
t
t
53
68
55
57
t
A
+
CC - 16 +
CC 9 +
SR –
SR –
t
C
+
t
min.
F
Max. CPU Clock
(100 ns at 20 MHz CPU clock without waitstates)
t
F
= 20 MHz
60
t
F
max.
30 +
5 +
–
–
t
F
t
F
1 / 2TCL = 1 to 20 MHz
min.
–
–
- 16 +
TCL - 16
+
Variable CPU Clock
t
F
t
F
max.
2TCL - 20
+ 2
1)
TCL - 20
+ 2
1)
–
–
t
t
A
A
V2.0, 2000-12
+
+
t
t
F
F
C165
Unit
ns
ns
ns
ns