PIC16C74-10I/P Microchip Technology, PIC16C74-10I/P Datasheet - Page 108

• Manufacturer Part Number: PIC16C74-10I/P
• Description: MICRO CTRL 4K 10MHZ OTP ET 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C74-10I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

PIC16C7X
12.2.2
The receiver block diagram is shown in Figure 12-10.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at F
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled
(PIE1<5>). Flag bit RCIF is a read only bit which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
FIGURE 12-10: USART RECEIVE BLOCK DIAGRAM
FIGURE 12-11: ASYNCHRONOUS RECEPTION
DS30390E-page 108
RX (pin)
Rcv shift
reg
Rcv buffer reg
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
USART ASYNCHRONOUS RECEIVER
by
RC7/RX/DT
causing the OERR (overrun) bit to be set.
setting/clearing
Baud Rate Generator
Start
x64 Baud Rate CLK
bit
OSC
SPBRG
Pin Buffer
and Control
bit0
SPEN
.
bit1
enable
bit
bit7/8
Data
Recovery
Interrupt
RCIE
Stop
bit
CREN
WORD 1
RCREG
or
Start
64
16
bit
bit0
RCIF
double buffered register, i.e. it is a two deep FIFO. It is
possible for two bytes of data to be received and trans-
ferred to the RCREG FIFO and a third byte begin shift-
ing to the RSR register. On the detection of the STOP
bit of the third byte, if the RCREG register is still full
then overrun error bit OERR (RCSTA<1>) will be set.
The word in the RSR will be lost. The RCREG register
can be read twice to retrieve the two bytes in the FIFO.
Overrun bit OERR has to be cleared in software. This
is done by resetting the receive logic (CREN is cleared
and then set). If bit OERR is set, transfers from the
RSR register to the RCREG register are inhibited, so it
is essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a stop bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG, will load bits RX9D and FERR with new
values, therefore it is essential for the user to read the
RCSTA register before reading RCREG register in
order not to lose the old FERR and RX9D information.
RCIE
RX9
MSb
Stop
RX9D
(8)
bit7/8
WORD 2
RCREG
OERR
7
Stop
RSR register
bit
RCREG register
8
Data Bus
Start
bit
1997 Microchip Technology Inc.
1
FERR
0
Start
LSb
bit7/8
FIFO
Stop
bit