PIC16C74-10I/P Microchip Technology, PIC16C74-10I/P Datasheet - Page 144

• Manufacturer Part Number: PIC16C74-10I/P
• Description: MICRO CTRL 4K 10MHZ OTP ET 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C74-10I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

PIC16C7X
14.7
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction. Dur-
ing normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled
(Section 14.1).
14.7.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, V
DC specs). If longer time-out periods are desired, a
FIGURE 14-18: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 14-19: SUMMARY OF WATCHDOG TIMER REGISTERS
DS30390E-page 144
Address
2007h
81h,181h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 14-1, and Figure 14-2 for operation of these bits.
Note: PSA and PS2:PS0 are bits in the OPTION register.
DD
Watchdog Timer (WDT)
WDT PERIOD
Applicable Devices
72 73 73A 74 74A 76 77
and process variations from part to part (see
by
Name
Config. bits
OPTION
clearing
WDT Timer
Enable Bit
WDT
configuration
RBPU
Bit 7
From TMR0 Clock Source
(Figure 7-6)
(1)
BODEN
INTEDG
bit
Bit 6
0
1
WDTE
(1)
PSA
M
U
X
T0CS
Bit 5
CP1
T0SE
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET con-
dition.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
14.7.2
It should also be taken into account that under worst
case conditions (V
max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
Bit 4
CP0
0
Note:
Time-out
8 - to - 1 MUX
MUX
WDT
Postscaler
WDT PROGRAMMING CONSIDERATIONS
PWRTE
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
1
Bit 3
PSA
8
(1)
DD
PSA
To TMR0 (Figure 7-6)
= Min., Temperature = Max., and
WDTE
Bit 2
PS2
1997 Microchip Technology Inc.
PS2:PS0
FOSC1
Bit 1
PS1
FOSC0
Bit 0
PS0