PIC16C74-10I/P Microchip Technology, PIC16C74-10I/P Datasheet - Page 180

• Manufacturer Part Number: PIC16C74-10I/P
• Description: MICRO CTRL 4K 10MHZ OTP ET 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C74-10I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

PIC16C7X
FIGURE 17-10: I
TABLE 17-9:
DS30390E-page 180
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
Applicable Devices 72 73 73A 74 74A 76 77
Parameter
No.
100
101
102
103
106
107
109
110
90
91
92
2: A fast-mode (400 kHz) I
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
tsu;DAT
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
T
released.
SDA
Out
SDA
In
SCL
R
max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I
T
T
T
T
T
Note: Refer to Figure 17-1 for load conditions
T
T
HD
HD
SU
SU
SU
Sym
T
T
HIGH
LOW
T
Cb
T
BUF
AA
:
:
:
:
R
:
F
STA
STA
DAT
DAT
STO
I
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
2
2
C BUS DATA TIMING
C BUS DATA REQUIREMENTS
Characteristic
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall time 100 kHz mode
START condition
setup time
START condition hold
time
Data input hold time
Data input setup time
STOP condition setup
time
Output valid from
clock
Bus free time
Bus capacitive loading
90
103
91
2
C-bus device can be used in a standard-mode (100 kHz)S I
109
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100
106
101
109
20 + 0.1Cb
20 + 0.1Cb
1.5T
1.5T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
107
CY
CY
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C bus specification) before the SCL line is
Units
2
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
C-bus system, but the requirement
s
s
s
s
s
s
s
s
s
s
s
s
s
1997 Microchip Technology Inc.
92
Device must operate at a mini-
mum of 1.5 MHz
Device must operate at a mini-
mum of 10 MHz
Device must operate at a mini-
mum of 1.5 MHz
Device must operate at a mini-
mum of 10 MHz
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission can
start
102
110
Conditions