PIC16C65A/JW Microchip Technology, PIC16C65A/JW Datasheet - Page 18
![IC MCU EPROM 4KX14 PWM 40CDIP](/photos/6/63/66338/150-40-cdip_sml.jpg)
PIC16C65A/JW
Manufacturer Part Number
PIC16C65A/JW
Description
IC MCU EPROM 4KX14 PWM 40CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16LC62A-04SP.pdf
(337 pages)
4.PIC16C65A-20P.pdf
(8 pages)
5.PIC16C65A-20P.pdf
(4 pages)
Specifications of PIC16C65A/JW
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
EPROM, UV
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-CDIP (0.600", 15.24mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C65A/JW
Manufacturer:
ON
Quantity:
4 300
Company:
Part Number:
PIC16C65A/JW
Manufacturer:
MIC
Quantity:
60
Company:
Part Number:
PIC16C65A/JW
Manufacturer:
MIC
Quantity:
60
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16LC62A-04SP PDF datasheet #3
- PIC16C65A-20P PDF datasheet #4
- PIC16C65A-20P PDF datasheet #5
- Current page: 18 of 337
- Download datasheet (3Mb)
PIC16C6X
3.1
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3, and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clock and instruction execution flow is
shown in Figure 3-5.
FIGURE 3-5:
EXAMPLE 3-1:
DS30234D-page 18
1. MOVLW 55h
2. MOVWF PORTB
3. CALL
4. BSF
5. Instruction @ address SUB_1
(Program counter)
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
OSC2/CLKOUT
Clocking Scheme/Instruction Cycle
(RC mode)
SUB_1
PORTA, BIT3 (Forced NOP)
OSC1
Q4
PC
Q2
Q3
Q1
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC-1)
Fetch INST (PC)
Q2
Fetch 1
Tcy0
PC
Q3
Q4
Execute 1
Fetch 2
Tcy1
Q1
Fetch INST (PC+1)
Execute INST (PC)
Q2
Execute 2
Fetch 3
PC+1
Tcy2
3.2
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3, and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q3
Q4
Execute 3
Instruction Flow/Pipelining
Fetch 4
Tcy3
Q1
Execute INST (PC+1)
Fetch INST (PC+2)
Fetch SUB_1 Execute SUB_1
Q2
PC+2
Flush
Tcy4
1997 Microchip Technology Inc.
Q3
Q4
Tcy5
Internal
Phase
Clock
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