PIC16C65A/JW Microchip Technology, PIC16C65A/JW Datasheet - Page 99
![IC MCU EPROM 4KX14 PWM 40CDIP](/photos/6/63/66338/150-40-cdip_sml.jpg)
PIC16C65A/JW
Manufacturer Part Number
PIC16C65A/JW
Description
IC MCU EPROM 4KX14 PWM 40CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16LC62A-04SP.pdf
(337 pages)
4.PIC16C65A-20P.pdf
(8 pages)
5.PIC16C65A-20P.pdf
(4 pages)
Specifications of PIC16C65A/JW
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
EPROM, UV
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-CDIP (0.600", 15.24mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
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Manufacturer:
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- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16LC62A-04SP PDF datasheet #3
- PIC16C65A-20P PDF datasheet #4
- PIC16C65A-20P PDF datasheet #5
- Current page: 99 of 337
- Download datasheet (3Mb)
11.5
The SSP module in I
functions, except general call support, and provides
interrupts on start and stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the standard mode specifica-
tions as well as 7-bit and 10-bit addressing. Two pins
are used for data transfer. These are the RC3/SCK/
SCL pin, which is the clock (SCL), and the RC4/SDI/
SDA pin, which is the data (SDA). The user must con-
figure these pins as inputs or outputs through the
TRISC<4:3> bits. The SSP module functions are
enabled by setting SSP Enable bit SSPEN (SSP-
CON<5>).
FIGURE 11-24: SSP BLOCK DIAGRAM
The SSP module has five registers for I
These are the:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
• SSP Address Register (SSPADD)
RC3/SCK/SCL
1997 Microchip Technology Inc.
RC4/
sible
SDI/
SDA
SSP I
2
Read
clock
C Operation
shift
(I
2
MSb
2
C MODE)
C mode fully implements all slave
Stop bit detect
Match detect
SSPADD reg
SSPBUF reg
SSPSR reg
Start and
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
LSb
Write
(SSPSTAT reg)
data bus
2
Internal
C operation.
Set, Reset
S, P bits
Addr Match
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, specifies if the received byte was
data or address if the next byte is the completion of 10-
bit address, and if this will be a read or write data trans-
fer. The SSPSTAT register is read only.
The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.
The SSPADD register holds the slave address. In 10-bit
mode, the user first needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
stop bit interrupts enabled
stop bit interrupts enabled
idle
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address), with start and
C Slave mode (10-bit address), with start and
C Firmware controlled Master Mode, slave is
2
C mode, with the SSPEN bit set,
2
C modes to be selected:
PIC16C6X
DS30234D-page 99
2
C opera-
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