PIC12C672/JW Microchip Technology, PIC12C672/JW Datasheet - Page 331
![IC MCU EPROM 2KX14 A/D 8CDIP](/photos/12/43/124388/pic12c672_jw_sml.jpg)
PIC12C672/JW
Manufacturer Part Number
PIC12C672/JW
Description
IC MCU EPROM 2KX14 A/D 8CDIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672/JW
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
EPROM, UV
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-CDIP (0.300", 7.62mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-
Other names
Q395827
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12C672/JW
Manufacturer:
MICKO
Quantity:
2 100
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17.4.18.3 Bus Collision During a STOP Condition
1997 Microchip Technology Inc.
SDA
SCL
PEN
BCLIF
P
SSPIF
SSPIF
BCLIF
SDA
PEN
SCL
P
Bus collision occurs during a STOP condition if:
a)
b)
The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is
allow to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded
with SSPADD<6:0> and counts down to 0. After the BRG times out SDA is sampled. If SDA is
sampled low, a bus collision has occurred. This is due to another master attempting to drive a
data '0'
collision occurs. This is another case of another master attempting to drive a data '0'
(Figure
Figure 17-40: Bus Collision During a STOP Condition (Case 1)
Figure 17-41: Bus Collision During a STOP Condition (Case 2)
After the SDA pin has been de-asserted and allowed to float high, SDA is sampled low
after the BRG has timed out.
After the SCL pin is de-asserted, SCL is sampled low before SDA goes high.
(Figure
17-41).
Assert SDA
T
SDA asserted low
BRG
17-40). If the SCL pin is sampled low before SDA is allowed to float high, a bus
T
BRG
Preliminary
T
BRG
T
BRG
Section 17. MSSP
SCL goes low before SDA goes high
Set BCLIF
T
BRG
T
BRG
DS31017A-page 17-55
'0'
'0'
SDA sampled
low after T
Set BCLIF
'0'
'0'
BRG
,
17
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