PIC12C672/JW Microchip Technology, PIC12C672/JW Datasheet - Page 605
![IC MCU EPROM 2KX14 A/D 8CDIP](/photos/12/43/124388/pic12c672_jw_sml.jpg)
PIC12C672/JW
Manufacturer Part Number
PIC12C672/JW
Description
IC MCU EPROM 2KX14 A/D 8CDIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672/JW
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
EPROM, UV
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-CDIP (0.300", 7.62mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-
Other names
Q395827
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12C672/JW
Manufacturer:
MICKO
Quantity:
2 100
- Current page: 605 of 688
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Figure 30-19: Example 8-bit A/D Conversion Timing Waveforms
Table 30-31:
Note 1: ADRES register may be read on the following T
Param
1997 Microchip Technology Inc.
No.
130
131
132
134
136
135
Note 1: If the A/D clock source is selected as RC, a time of T
†
§ This specification ensured by design.
A/D DATA
SAMPLE
tested.
A/D CLK
Data in “Typ” column is at 5V, 25 C unless otherwise stated. These parameters are for design guidance only and are not
ADRES
Symbol Characteristic
See the
BSF ADCON0, GO
T
T
T
T
ADIF
T
T
SWC
CNV
ACQ
AMP
GO
GO
Q4
AD
allows the SLEEP instruction to be executed.
Example 8-bit A/D Conversion Requirements
“8-bit A/D Converter”
A/D clock period PIC16CXXX
Conversion time
(not including S/H time) (Note 1)
Acquisition time
Q4 to A/D clock start
Amplifier settling time (Note 2)
Switching Time from
convert
132
Section 30. Electrical Specifications
sample
(T
OSC
/2)
PIC16LCXXX
PIC16CXXX
PIC16LCXXX
7
(1)
section for minimum requirements.
6
OLD_DATA
Note 2
5
Min
1.6
2.0
2.0
3.0
1 §
11
—
SAMPLING STOPPED
5
1
CY
4
cycle.
2T
Typ†
131
130
4.0
6.0
20
—
—
—
—
—
—
OSC
§
CY
3
is added before the A/D clock starts. This
Max
6.0
9.0
1 §
11
—
—
—
—
—
—
2
Units
T
T
1
—
AD
AD
s
s
s
s
s
s
s
T
T
A/D RC Mode
A/D RC Mode
The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
C
If the A/D clock source is selected
as RC, a time of T
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
This may be used if the “new”
input voltage has not changed by
more than 1LSb (i.e. 5 mV @
5.12V) from the last sampled volt-
age (as stated on C
1 T
0
OSC
OSC
HOLD
CY
).
based, V
based, V
NEW_DATA
Conditions
DONE
DS31030A-page 30-35
REF
REF
CY
HOLD
full range
is added
3.0V
).
30
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