Errata
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13. Power Consumption when Using Slowly Rising Power Supply
12. Releasing Reset Condition without Clock
11. Wake-up from Power-save Executes Instructions before Interrupt
10. The SPI Can Send Wrong Byte
Power Consumption when Using Slowly Rising Power Supply
Releasing Reset Condition without Clock
Wake-up from Power-save Executes Instructions before Interrupt
SPI Can Send Wrong Byte
Wrong Clearing of EXTRF in MCUSR
Reset during EEPROM Write
SPI Interrupt Flag Can be Undefined after Reset
Skip Instruction with Interrupts
Signature Bytes
Read Back Value during EEPROM Polling
MISO Active during In-System Programming
The ADC Has no Free-running Mode
UART Loses Synchronization if RXD Line is Low when UART Receive is Disabled
If the power supply rises slowly upon start-up (slower than 10 ms rise time), the
power consumption in sleep modes may exceed the specification.
Problem Fix/Workaround
The device behaves functionally correct, and no actions need to be taken if power
consumption is acceptable. To reduce power consumption, make sure the power
supply has a sufficiently fast rise time.
If an external reset or a watchdog reset occurs while the clock is stopped and the
reset is released before the clock is restarted, the internal reset will time-out after
the start-up delay which is independent of the external clock. If no external clock
pulses are present in the period when internal reset is active, the reset does cor-
rectly cause tri-stating of the I/O while the reset is held. However, if the internal
reset is released before the clock starts running, the part does not clear I/O regis-
ters, nor set PC to 0x00. Here, stopping the clock refers to gating the external
clock input. Power-down and Power-save mode do not have this issue.
Problem Fix/Workaround
Make sure the clock is running whenever an external reset can be expected. If the
watchdog is used, never stop an external clock.
When waking up from Power-save, some instructions are executed before the
interrupt is called. If the device is woken up by an external interrupt, two instruc-
tion cycles are executed. If it is woken up by the asynchronous timer, three
instructions are executed before the interrupt.
Problem Fix/Workaround
Make sure that the first two or three instructions following sleep are not dependent
on the executed interrupt.
If the SPI is in Master mode, it will restart the old transfer if new data is written on
the same clock edge as the previous transfer is finished.
Problem Fix/Workaround
When writing to the SPI, first wait until it is ready, then write the byte to transmit.
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega103(L)
Rev. L
Errata Sheet
Rev. 1436C–09/01
1