PIC16C923-08/SP Microchip Technology, PIC16C923-08/SP Datasheet - Page 103
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PIC16C923-08/SP
Manufacturer Part Number
PIC16C923-08/SP
Description
IC MCU 64 LD 8MHZ 4K OTP 64-SDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F818-ISO.pdf
(6 pages)
2.PIC16C923-04L.pdf
(189 pages)
3.PIC16C923-04L.pdf
(10 pages)
Specifications of PIC16C923-08/SP
Core Processor
PIC
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
64-SDIP (0.750", 19.05mm)
For Use With
AC164025 - MODULE SKT PROMATEII 64DIPDVA16XP640 - ADAPTER DEVICE FOR MPLAB-ICE
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Data Converters
-
- Current page: 103 of 189
- Download datasheet (2Mb)
14.0
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of
real-time applications. The PIC16CXXX family has a
host of such features intended to maximize system reli-
ability, minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection. These are:
• Oscillator selection
• Reset
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming
The PIC16CXXX has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
FIGURE 14-1: CONFIGURATION WORD
1997 Microchip Technology Inc.
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
bit13
bit 13-8 CP1:CP0 Code protection bits
bit 6:
bit 3:
bit 2:
bit 1-0:
Note 1: All of the CP1:CP0 bits have to be given the same value to enable the code protection scheme listed.
CP1
5-4: 11 = Code protection off
SPECIAL FEATURES OF THE
CPU
CP0
10 = Upper half of program memory code protected
01 = Upper 3/4 of program memory code protected
00 = All memory is code protected
Unimplemented: Read as '1'
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
CP1
CP0
CP1
CP0
(1)
—
—
CP1
CP0
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in reset while the power sup-
ply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
14.1
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h -
3FFFh), which can be accessed only during program-
ming.
PWRTE WDTE FOSC1 FOSC0
Configuration Bits
PIC16C9XX
bit0
Register:
Address
DS30444E - page 103
CONFIG
2007h
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