PIC16C923-08/SP Microchip Technology, PIC16C923-08/SP Datasheet - Page 63
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PIC16C923-08/SP
Manufacturer Part Number
PIC16C923-08/SP
Description
IC MCU 64 LD 8MHZ 4K OTP 64-SDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F818-ISO.pdf
(6 pages)
2.PIC16C923-04L.pdf
(189 pages)
3.PIC16C923-04L.pdf
(10 pages)
Specifications of PIC16C923-08/SP
Core Processor
PIC
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
64-SDIP (0.750", 19.05mm)
For Use With
AC164025 - MODULE SKT PROMATEII 64DIPDVA16XP640 - ADAPTER DEVICE FOR MPLAB-ICE
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Data Converters
-
- Current page: 63 of 189
- Download datasheet (2Mb)
11.0
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
1997 Microchip Technology Inc.
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W-0 R/W-0
SMP
SYNCHRONOUS SERIAL
PORT (SSP) MODULE
SMP: SPI data input sample phase
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
CKE: SPI Clock Edge Select (Figure 11-5, Figure 11-6, and Figure 11-7)
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit (I
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
S: Start bit (I
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
R/W: Read/Write bit information (I
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
UA: Update Address (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
CKE
detected last)
detected last)
R-0
D/A
2
C mode only)
2
2
C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit was
C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit was
2
R-0
C modes)
P
2
C mode only)
2
C mode only)
R-0
S
2
C mode only)
R/W
R-0
play drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
Refer to Application Note AN578, "Use of the SSP
Module in the I
R-0
UA
R-0
BF
2
bit0
C Multi-Master Environment."
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n =Value at POR reset
PIC16C9XX
2
C)
read as ‘0’
DS30444E - page 63
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