PIC16C923-08/SP Microchip Technology, PIC16C923-08/SP Datasheet - Page 64
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PIC16C923-08/SP
Manufacturer Part Number
PIC16C923-08/SP
Description
IC MCU 64 LD 8MHZ 4K OTP 64-SDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F818-ISO.pdf
(6 pages)
2.PIC16C923-04L.pdf
(189 pages)
3.PIC16C923-04L.pdf
(10 pages)
Specifications of PIC16C923-08/SP
Core Processor
PIC
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
64-SDIP (0.750", 19.05mm)
For Use With
AC164025 - MODULE SKT PROMATEII 64DIPDVA16XP640 - ADAPTER DEVICE FOR MPLAB-ICE
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Data Converters
-
- Current page: 64 of 189
- Download datasheet (2Mb)
PIC16C9XX
FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
DS30444E - page 64
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
WCOL
R/W-0
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even
if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each
new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
In I
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care"
in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
0000 = SPI master mode, clock = F
0001 = SPI master mode, clock = F
0010 = SPI master mode, clock = F
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0110 = I
0111 = I
1011 = I
1110 = I
1111 = I
SSPOV
R/W-0
2
2
2
C mode
C mode
C mode
2
2
2
2
2
C slave mode, 7-bit address
C slave mode, 10-bit address
C Firmware controlled master mode (slave idle)
C slave mode, 7-bit address with start and stop bit interrupts enabled
C slave mode, 10-bit address with start and stop bit interrupts enabled
SSPEN
R/W-0
R/W-0
CKP
SSPM3
R/W-0
OSC
OSC
OSC
/4
/16
/64
SSPM2
R/W-0
SSPM1
R/W-0
SSPM0
R/W-0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n =Value at POR reset
1997 Microchip Technology Inc.
read as ‘0’
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