PIC16C924-08/SP Microchip Technology, PIC16C924-08/SP Datasheet - Page 65
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PIC16C924-08/SP
Manufacturer Part Number
PIC16C924-08/SP
Description
IC MCU 64 LD 8MHZ 4K OTP 64-SDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C923-04L.pdf
(189 pages)
4.PIC16LC924-04L.pdf
(10 pages)
Specifications of PIC16C924-08/SP
Core Processor
PIC
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
64-SDIP (0.750", 19.05mm)
For Use With
AC164025 - MODULE SKT PROMATEII 64DIPDVA16XP640 - ADAPTER DEVICE FOR MPLAB-ICE
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16C923-04L PDF datasheet #3
- PIC16LC924-04L PDF datasheet #4
- Current page: 65 of 189
- Download datasheet (2Mb)
11.1
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI) RC4/SDI
• Serial Clock (SCK) RC3/SCK
Additionally a fourth pin may be used when in a slave
mode of operation:
• Slave Select (SS) RA5/AN4/SS (the AN4 function
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specified:
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Clock edge (output data on rising/falling edge of
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
The SSP consists of a transmit/receive Shift Register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register. Then
(SSPSTAT<0>) and interrupt flag bit SSPIF (PIR1<3>)
are set. This double buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit WCOL
(SSPCON<7>) will be set. User software must clear the
WCOL bit so that it can be determined if the following
write(s) to the SSPBUF register completed success-
fully. When the application software is expecting to
receive valid data, the SSPBUF should be read before
the next byte of data to transfer is written to the
SSPBUF. Buffer full bit BF (SSPSTAT<0>) indicates
when SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
bit BF is cleared. This data may be irrelevant if the SPI
is only a transmitter. Generally the SSP Interrupt is
used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or writ-
ten. If the interrupt method is not going to be used, then
software polling can be done to ensure that a write col-
lision does not occur. Example 11-1 shows the loading
of the SSPBUF (SSPSR) for data transmission. The
shaded instruction is only required if the received data
is meaningful.
1997 Microchip Technology Inc.
is implemented on the PIC16C924 only)
SCK)
SPI Mode
the
buffer
full
detect
bit
BF
EXAMPLE 11-1: LOADING THE SSPBUF
LOOP BTFSS SSPSTAT, BF
The block diagram of the SSP module, when in SPI
mode (Figure 11-3), shows that the SSPSR is not
directly readable or writable, and can only be accessed
from addressing the SSPBUF register. Additionally, the
SSP status register (SSPSTAT) indicates the various
status conditions.
FIGURE 11-3: SSP BLOCK DIAGRAM
RC4/SDI/SDA
RC5/SDO
RA5/AN4/SS
RC3/SCK/
SCL
BCF
BSF
GOTO
BCF
MOVF
MOVWF RXDATA
MOVF
MOVWF SSPBUF
STATUS, RP1
STATUS, RP0
LOOP
STATUS, RP0
SSPBUF, W
TXDATA, W
Read
SS Control
(SPI MODE)
Select
TRISC<3>
Edge
Enable
SSPM3:SSPM0
bit0
Select
Edge
(SSPSR) REGISTER
SSPBUF reg
SSPSR reg
PIC16C9XX
Clock Select
4
;Select Bank1
;
;Has data been
;received
;(transmit
;complete)?
;No
;Select Bank0
;W reg = contents
; of SSPBUF
;Save in user RAM
;W reg = contents
; of TXDATA
;New data to xmit
2
DS30444E - page 65
Write
Prescaler
4, 16, 64
clock
shift
TMR2 output
data bus
Internal
2
T
CY
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