PIC17C42A-33I/PQ Microchip Technology, PIC17C42A-33I/PQ Datasheet - Page 26
![IC MCU OTP 2KX16 PWM 44-MQFP](/photos/6/59/65984/150-44-pqfp_sml.jpg)
PIC17C42A-33I/PQ
Manufacturer Part Number
PIC17C42A-33I/PQ
Description
IC MCU OTP 2KX16 PWM 44-MQFP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C42A-16P.pdf
(241 pages)
3.PIC17C42A-16P.pdf
(4 pages)
Specifications of PIC17C42A-33I/PQ
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
33
Program Memory Size
4KB (2K x 16)
Program Memory Type
OTP
Ram Size
232 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-MQFP, 44-PQFP
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
232 B
Interface Type
SCI, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
33
Number Of Timers
8
Operating Supply Voltage
2.5 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
For Use With
AC164316 - MODULE SKT MPLAB PM3 44MQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C42A-33I/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC17C4X
5.5
The external interrupt on the RA0/INT pin is edge trig-
gered. Either the rising edge, if INTEDG bit
(T0STA<7>) is set, or the falling edge, if INTEDG bit is
clear. When a valid edge appears on the RA0/INT pin,
the INTF bit (INTSTA<4>) is set. This interrupt can be
disabled by clearing the INTE control bit (INTSTA<0>).
The INT interrupt can wake the processor from SLEEP.
See Section 14.4 for details on SLEEP operation.
5.6
An overflow (FFFFh
T0IF (INTSTA<5>) bit. The interrupt can be enabled/
disabled by setting/clearing the T0IE control bit
(INTSTA<1>). For operation of the Timer0 module, see
Section 11.0.
FIGURE 5-5:
DS30412C-page 26
RA1/T0CKI
System Bus
RA0/INT or
Instruction
executed
Instruction
GLINTD
Fetched
T0CKIF
INTF or
OSC1
OSC2
PC
RA0/INT Interrupt
TMR0 Interrupt
Q1
Q2
PC
PC
INT PIN / T0CKI PIN INTERRUPT TIMING
Q3 Q4
Inst (PC)
0000h) in TMR0 will set the
Q1
Inst (PC)
Q2
Addr
Q3 Q4
PC + 1
Inst (PC+1)
Q1
Dummy
Addr
Q2
Q3 Q4
Inst (PC+1)
Q1
Addr (Vector)
Dummy
Addr
Q2
5.7
The external interrupt on the RA1/T0CKI pin is edge
triggered. Either the rising edge, if the T0SE bit
(T0STA<6>) is set, or the falling edge, if the T0SE bit is
clear. When a valid edge appears on the RA1/T0CKI
pin, the T0CKIF bit (INTSTA<6>) is set. This interrupt
can be disabled by clearing the T0CKIE control bit
(INTSTA<2>). The T0CKI interrupt can wake up the
processor from SLEEP. See Section 14.4 for details on
SLEEP operation.
5.8
The peripheral interrupt flag indicates that at least one
of the peripheral interrupts occurred (PEIF is set). The
PEIF bit is a read only bit, and is a bit wise OR of all the
flag bits in the PIR register AND’ed with the corre-
sponding enable bits in the PIE register. Some of the
peripheral interrupts can wake the processor from
SLEEP. See Section 14.4 for details on SLEEP opera-
tion.
Inst (Vector)
Q3 Q4
Q1
T0CKI Interrupt
Peripheral Interrupt
Addr
Q2
YY
Q3 Q4
RETFIE
Q1
Addr
1996 Microchip Technology Inc.
RETFIE
Q2
YY + 1
Inst (YY + 1)
Q3 Q4
Q1
Q2
Dummy
PC + 1
Q3 Q4
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