AT90LS4433-4PI Atmel, AT90LS4433-4PI Datasheet - Page 52
![IC MCU 4K FLSH 4MHZ A/D LV 28DIP](/photos/7/21/72189/453-28-dip_sml.jpg)
AT90LS4433-4PI
Manufacturer Part Number
AT90LS4433-4PI
Description
IC MCU 4K FLSH 4MHZ A/D LV 28DIP
Manufacturer
Atmel
Series
AVR® 90LSr
Datasheet
1.AT90S4433-8AC.pdf
(126 pages)
Specifications of AT90LS4433-4PI
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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SPI Status Register – SPSR
SPI Data Register – SPDR
52
AT90S/LS4433
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is gener-
ated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and
is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set
(one), then by accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Reg-
ister with WCOL set (one), and then by accessing the SPI Data Register.
• Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S4433 and will always read as zero.
The SPI interface on the AT90S4433 is also used for Program memory and EEPROM
downloading or uploading. See page 93 for Serial Programming and verification.
The SPI Data Register is a read/write register used for data transfer between the Regis-
ter File and the SPI Shift Register. Writing to the register initiates data transmission.
Reading the register causes the Shift Register Receive buffer to be read.
Bit
$0E ($2E)
Read/Write
Initial Value
Bit
$0F ($2F)
Read/Write
Initial Value
SPIF
MSB
R/W
R
X
7
0
7
WCOL
R/W
R
X
6
0
6
R/W
R
X
5
–
0
5
R/W
R
X
4
–
0
4
R/W
R
3
–
0
3
X
R/W
R
X
2
–
0
2
R/W
R
X
1
–
0
1
LSB
R/W
R
0
–
0
0
X
1042H–AVR–04/03
Undefined
SPSR
SPDR
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