ATMEGA323-8PI Atmel, ATMEGA323-8PI Datasheet - Page 50

• Manufacturer Part Number: ATMEGA323-8PI
• Description: IC AVR MCU 32K 8MHZ IND 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA3238PI

PWM Modes (Up/Down and
Overflow)
50
ATmega323(L)
The two different PWM modes are selected by the CTC0 or CTC2 bit in the
Timer/Counter Control Registers –TCCR0 or TCCR2 respectively.
If CTC0/CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an
up/down counter, counting up from $00 to $FF, where it turns and counts down again to
zero before the cycle is repeated. When the counter value matches the contents of the
Output Compare Register, the PB3(OC0/PWM0) or PD7(OC2/PWM2) pin is set or
cleared according to the settings of the COMn1/COMn0 bits in the Timer/Counter Con-
trol Registers TCCR0 or TCCR2.
If CTC0/CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start
counting from $00 after reaching $FF. The PB3(OC0/PWM0) or PD7(OC2/PWM2) pin
will be set or cleared according to the settings of COMn1/COMn0 on a Timer/Counter
overflow or when the counter value matches the contents of the Output Compare Regis-
ter. Refer to Table 15 for details.
Table 15. Compare Mode Select in PWM Mode
Note:
Note that in PWM mode, the value to be written to the Output Compare Register is first
transferred to a temporary location, and then latched into the OCR when the
Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses
(glitches) in the event of an unsynchronized OCR0 or OCR2 write. See Figure 34 and
Figure 35 for examples.
CTCn
0
0
0
0
1
1
1
1
1. n = 0 or 2
COMn1
0
0
1
1
0
0
1
1
COMn0
0
1
0
1
0
1
0
1
Effect on Compare Pin
Not connected
Not connected
Cleared on Compare Match, up-counting. Set on
Compare Match, down-counting (non-inverted
PWM)
Cleared on Compare Match, down-counting. Set
on Compare Match, up-counting (inverted PWM)
Not connected
Not connected
Cleared on Compare Match, set on overflow
Set on Compare Match, cleared on overflow
(1)
1457G–AVR–09/03
Frequency
f
f
f
f
TCK0/2
TCK0/2
TCK0/2
TCK0/2
/510
/510
/256
/256