ATMEGA161L-4PI Atmel, ATMEGA161L-4PI Datasheet
ATMEGA161L-4PI
Specifications of ATMEGA161L-4PI
Related parts for ATMEGA161L-4PI
ATMEGA161L-4PI Summary of contents
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... Operating Voltages – 2.7V - 5.5V for the ATmega161L – 4.0V - 5.5V for the ATmega161 • Speed Grades – MHz for the ATmega161L – MHz for the ATmega161 • Commercial and Industrial Temperature Ranges Disclaimer Typical values contained in this data sheet are based on simulations and characteriza- tion of other AVR microcontrollers manufactured on the same process technology ...
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Pin Configuration ATmega161(L) 2 PDIP (OC0/T0) PB0 1 (OC2/T1) PB1 2 (RXD1/AIN0) PB2 3 (TXD1/AIN1) PB3 4 (SS) PB4 5 (MOSI) PB5 6 (MISO) PB6 7 (SCK) PB7 8 RESET 9 (RXD0) PD0 10 (TXD0) PD1 11 (INT0) PD2 12 ...
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... Boot Block and an ISP through the SPI port using a conven- tional non-volatile Memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel ATmega161 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications ...
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Block Diagram ATmega161(L) 4 Figure 1. The ATmega161 Block Diagram PA0-PA7 VCC PORTA DRIVERS GND DATA REGISTER DATA DIR. PORTA REG. PORTA PROGRAM STACK COUNTER POINTER PROGRAM SRAM FLASH INSTRUCTION GENERAL REGISTER PURPOSE REGISTERS X INSTRUCTION Y DECODER Z CONTROL ...
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Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E (PE2..PE0) RESET XTAL1 XTAL2 1228D–AVR–02/07 Supply voltage. Ground. Port 8-bit bi-directional I/O port. Port pins can provide internal pull-up ...
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Crystal Oscillator ATmega161(L) 6 XTAL1 and XTAL2 are input and output, respectively inverting amplifier that can be configured for use as an on-chip Oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may ...
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Architectural Overview 1228D–AVR–02/07 The fast-access Register File concept contains 32 x 8-bit general purpose working reg- isters with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. ...
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ATmega161( addition to the register operation, the conventional Memory Addressing modes can be used on the Register File. This is enabled by the fact that the Register File is assigned the 32 lowermost Data Space addresses ($00 - ...
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Figure 5. Memory Maps Program Memory Program Flash (8K x 16) A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All the different interrupts have ...
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The General Purpose Register File The X-register, Y-register and Z-register ATmega161(L) 10 Figure 6 shows the structure of the 32 general purpose working registers in the CPU. Figure 6. AVR CPU General Purpose Working Registers 7 General Purpose Working Registers ...
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ALU – Arithmetic Logic Unit Self-programmable Flash Program Memory EEPROM Data Memory 1228D–AVR–02/07 In the different Addressing modes, these address registers have functions as fixed dis- placement, automatic increment and decrement (see the descriptions for the different instructions). The high-performance ...
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SRAM Data Memory ATmega161(L) 12 Figure 8 shows how the ATmega161 SRAM memory is organized. Figure 8. SRAM Organization Register File … R29 R30 R31 I/O Registers $00 $01 $02 … $3D $3E $3F The lower 1120 ...
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Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr 1228D–AVR–02/07 The five different Addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. ...
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I/O Direct Data Direct ATmega161(L) 14 Operands are contained in registers r (Rr) and d (Rd). The result is stored in register d (Rd). Figure 11. I/O Direct Addressing Operand address is contained in six bits of ...
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Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement 1228D–AVR–02/07 Figure 13. Data Indirect with Displacement REGISTER Operand address is the result of the Y- or Z-register ...
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Data Indirect with Post- increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL ATmega161(L) 16 Figure 16. Data Indirect Addressing with Post-increment REGISTER The X-, Y-, or Z-register is incremented ...
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Relative Program Addressing, RJMP and RCALL Direct Program Addressing, JMP and CALL Memory Access Times and Instruction Execution Timing 1228D–AVR–02/07 Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). ...
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ATmega161(L) 18 Figure 21. The Parallel Instruction Fetches and Instruction Executions T1 System Clock Ø 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 22 shows the ...
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Memory 1228D–AVR–02/07 The I/O space definition of the ATmega161 is shown in Table 1. (1) Table 1. ATmega161 I/O Space I/O Address (SRAM Address) Name $3F($5F) SREG $3E ($5E) SPH $3D ($5D) SPL $3B ($5B) GIMSK $3A ($5A) GIFR ...
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ATmega161(L) 20 (1) Table 1. ATmega161 I/O Space I/O Address (SRAM Address) Name Function $1C ($3C) EECR EEPROM Control Register $1B($3B) PORTA Data Register, Port A $1A ($3A) DDRA Data Direction Register, Port A $19 ($39) PINA Input Pins, Port ...
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Status Register – SREG 1228D–AVR–02/07 All ATmega161 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general pur- pose working registers and the I/O ...
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Stack Pointer – SP Reset and Interrupt Handling ATmega161(L) 22 • Bit 2 N: Negative Flag – The Negative Flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set description for detailed information. ...
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Table 2. Reset and Interrupt Vectors Vector No. Program Address Source 1 $000 RESET 2 $002 INT0 3 $004 INT1 4 $006 INT2 5 $008 TIMER2 COMP 6 $00a TIMER2 OVF 7 $00c TIMER1 CAPT 8 $00e TIMER1 COMPA ...
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ATmega161(L) 24 $01a jmp $01c jmp $01e jmp $020 jmp $022 jmp $024 jmp $026 jmp $028 jmp ; $02a MAIN: ldi r16,high(RAMEND) ; Main program start $02b out SPH,r16 $02c ldi r16,low(RAMEND) $02d out SPL,r16 $02e <instr> … … ...
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Reset Sources 1228D–AVR–02/07 The ATmega161 has three sources of Reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). POT • External Reset. The MCU is reset when a low ...
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ATmega161(L) 26 Table 3. Reset Characteristics (V CC Symbol Parameter V Power-on Reset Threshold Voltage (rising) POT Power-on Reset Threshold Voltage (falling) V RESET Pin Threshold Voltage RST Note: 1. The Power-on Reset will not work unless the supply voltage ...
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Power-on Reset 1228D–AVR–02/07 A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec- tion level is nominally 1.4V (rising V the detection level. The POR circuit can be used to trigger the Start-up Reset, as well ...
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External Reset Watchdog Reset ATmega161( External Reset is generated by a low level on the RESET pin. Reset pulses longer than 500 ns will generate a Reset, even if the clock is not running. Shorter pulses are not ...
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MCU Status Register – MCUSR Interrupt Handling 1228D–AVR–02/07 The MCU Status Register provides information on which reset source caused an MCU Reset. Bit $34 ($54) – – – Read/Write Initial Value ...
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Interrupt Response Time General Interrupt Mask Register – GIMSK ATmega161(L) 30 Note that the Status Register is not automatically stored when entering an interrupt rou- tine or restored when returning from an interrupt routine. This must be handled by software. ...
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General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK 1228D–AVR–02/07 • Bits 4..0 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and always read as zero. Bit $3A ($5A) INTF1 ...
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ATmega161(L) 32 • Bit 5 OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable – When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt ...
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Timer/Counter Interrupt Flag Register – TIFR 1228D–AVR–02/07 Bit $38 ($58) TOV1 OCF1A OCIFB Read/Write R/W R/W R/W Initial Value • Bit 7 TOV1: Timer/Counter1 Overflow Flag – The TOV1 is set (one) when an ...
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External Interrupts MCU Control Register – MCUCR ATmega161(L) 34 Compare match InterruptA Enable) and the OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed. • Bit 1 TOV0: Timer/Counter0 Overflow Flag – The bit TOV0 is set (one) ...
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Sleep Enable (SE) bit just before the execution of the SLEEP instruction. • Bit 4 SM1: Sleep Mode Select Bit 1 – The SM1 bit, together with the SM0 control bit ...
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Extended MCU Control Register – EMCUCR Sleep Modes Idle Mode ATmega161(L) 36 The Extended MCU Control Register contains control bits for External Interrupt 2, Sleep mode bit and control bits for the external memory interface. Bit $36 ...
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Power-down Mode Power-save Mode 1228D–AVR–02/07 Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register (ACSR). This will reduce power consumption in Idle mode. ...
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Timer/Counters Timer/Counter Prescalers ATmega161(L) 38 The ATmega161 provides three general purpose Timer/Counters – two 8-bit T/Cs and one 16-bit T/C. Timer/Counter2 can optionally be asynchronously clocked from an exter- nal Oscillator. This Oscillator is optimized for use with a 32.768 ...
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Special Function IO Register – SFIOR 1228D–AVR–02/07 Figure 30. Timer/Counter2 Prescaler CK PCK2 TOSC1 AS2 PSR2 CS20 CS21 CS22 The clock source for Timer/Counter2 prescaler is named PCK2. PCK2 is by default con- nected to the main system clock (CK). ...
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Timer/Counters T/C0 and T/C2 ATmega161(L) 40 • Bit 0 PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 – When this bit is set (one), the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the ...
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Figure 32. Timer/Counter2 Block Diagram T/C2 OVER- FLOW IRQ TIMER INT. MASK TIMER INT. FLAG REGISTER (TIMSK) REGISTER (TIFR T/C CLEAR TIMER/COUNTER2 T/C CLK SOURCE (TCNT2) UP/DOWN 7 0 8-BIT COMPARATOR 7 0 OUTPUT COMPARE REGISTER2 (OCR2) ...
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Timer/Counter0 Control Register – TCCR0 Timer/Counter2 Control Register – TCCR2 ATmega161(L) 42 Bit $33 ($53) FOC0 PWM0 COM01 Read/Write R/W R/W R/W Initial Value Bit $27 ($47) FOC2 PWM2 COM21 Read/Write ...
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C, the timer will count as fol- lows if CTC0/CTC2 is set: ... | C ... When the prescaler is ...
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Timer Counter0 – TCNT0 Timer/Counter2 – TCNT2 Timer/Counter0 Output Compare Register – OCR0 Timer/Counter2 Output Compare Register – OCR2 Timer/Counters 0 and 2 in PWM Mode ATmega161(L) 44 Bit $32 ($52) MSB Read/Write R/W R/W R/W Initial ...
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PWM Modes (Up/Down and Overflow) 1228D–AVR–02/07 The two different PWM modes are selected by the CTC0 or CTC2 bit in the Timer/Counter Control Registers – TCCR0 or TCCR2, respectively. If CTC0/CTC2 is cleared and PWM mode is selected, the Timer/Counter ...
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ATmega161(L) 46 Figure 33. Effects of Unsynchronized OCR Latching in Up/Down Mode Compare Value changes Synchronized OCn Latch Compare Value changes Unsynchronized OCn Latch Figure 34. Effects of Unsynchronized OCR Latching in Overflow Mode. Synchronized OCn Latch Unsynchronized OCn Latch ...
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Asynchronous Status Register – ASSR 1228D–AVR–02/07 In up/down PWM mode, the Timer Overflow Flag (TOV0 or TOV2) is set when the counter advances from $00. In overflow PWM mode, the Timer Overflow Flag is set as in normal Timer/Counter mode. ...
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Asynchronous Operation of Timer/Counter2 ATmega161(L) 48 When Timer/Counter2 operates asynchronously, some considerations must be taken: • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might get corrupted. A safe procedure for ...
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Timer/Counter1 1228D–AVR–02/07 • Description of wake-up from Power-save mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake-up process is started on the following cycle of the timer clock, that is, the timer is always ...
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Timer/Counter1 Control Register A – TCCR1A ATmega161(L) 50 clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 16-bit Timer/Counter1 features both a high-resolution and a high-accuracy usage with the lower prescaling ...
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Bits 5, 4 COM1B1, COM1B0: Compare Output Mode1B, Bits 1 and 0 – The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B (Output ...
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Timer/Counter1 Control Register B – TCCR1B ATmega161(L) 52 • Bits 1..0 PWM11, PWM10: Pulse Width Modulator Select Bits – These bits select PWM operation of Timer/Counter1 as specified in Table 15. This mode is described on page 55. Table 15. ...
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Timer/Counter1 Register – TCNT1H AND TCNT1L 1228D–AVR–02/07 • Bits CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0 – The Clock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1. Table 16. Clock ...
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Timer/Counter1 Output Compare Register – OCR1AH AND OCR1AL Timer/Counter1 Output Compare Register – OCR1BH AND OCR1BL Timer/Counter1 Input Capture Register – ICR1H AND ICR1L ATmega161(L) 54 The Timer/Counter1 is realized up/down (in PWM mode) counter with ...
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Timer/Counter1 in PWM Mode 1228D–AVR–02/07 The Input Capture Register is a 16-bit read-only register. When the rising or falling edge (according to the Input Capture edge setting, ICES1) of the signal at the Input Capture pin (ICP) is detected, the ...
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ATmega161(L) 56 Table 18. Compare1 Mode Select in PWM Mode CTC1 COM1X1 COM1X0 Effect on OCX1 Not connected Not connected Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted ...
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Figure 38. Effects of Unsynchronized OCR1 Latching in Overflow Mode Synchronized OC1x Latch Unsynchronized OC1x Latch Note: 1. Note During the time between the write and the latch operation, a read from OCR1A or ...
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Watchdog Timer Watchdog Timer Control Register – WDTCR ATmega161(L) 58 The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz. This is the typical value 5V. See characterization data for typical values ...
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WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following proce- dure must be followed the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE ...
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EEPROM Read/Write Access EEPROM Address Register – EEARH and EEARL EEPROM Data Register – EEDR ATmega161(L) 60 The EEPROM Access Registers are accessible in the I/O space. The write access time is in the range of 1.9 - 3.4 ms, ...
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EEPROM Control Register – EECR 1228D–AVR–02/07 Bit $1C ($3C) – – – Read/Write Initial Value • Bits 7..4 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and ...
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Prevent EEPROM Corruption ATmega161(L) 62 bit. When EERE has been set, the CPU is halted for four cycles before the next instruc- tion is executed. The user should poll the EEWE bit before starting the read operation write ...
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Serial Peripheral Interface – SPI 1228D–AVR–02/07 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega161 and peripheral devices or between several AVR devices. The ATmega161 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer ...
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ATmega161(L) 64 The interconnection between Master and Slave CPUs with SPI is shown in Figure 41. The PB7(SCK) pin is the Clock Output in the Master mode and is the clock input in the Slave mode. Writing to the SPI ...
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SS Pin Functionality Data Modes 1228D–AVR–02/07 When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin configured as an output, the pin is a ...
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SPI Control Register – SPCR ATmega161(L) 66 Figure 43. SPI Transfer Format with CPHA = 1 and DORD = 0 Bit $0D ($2D) SPIE SPE DORD Read/Write R/W R/W R/W Initial Value • Bit ...
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SPI Status Register – SPSR 1228D–AVR–02/07 • Bits 1, 0 SPR1, SPR0: SPI Clock Rate Select 1 and 0 – These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect ...
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SPI Data Register – SPDR ATmega161(L) 68 Bit $0F ($2F) MSB Read/Write R/W R/W R/W Initial Value The SPI Data Register is a read/write register used for data transfer between the Regis- ter File ...
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UARTs Data Transmission 1228D–AVR–02/07 The ATmega161 features two full-duplex (separate Receive and Transmit Registers) Universal Asynchronous Receiver and Transmitters (UARTs). The main features are: • Baud Rate Generator Generates any Baud Rate • High Baud Rates at low XTAL Frequencies ...
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ATmega161(L) 70 • A new character has been written to UDRn before the stop bit from the previous character has been shifted out. The Shift Register is loaded when the stop bit of the character currently being transmitted has been ...
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Data Reception 1228D–AVR–02/07 Figure 45 shows a block diagram of the UART Receiver. Figure 45. UART Receiver BAUD x 16 BAUD RATE XTAL GENERATOR PIN CONTROL LOGIC PD0/ RXDn DATA RECOVERY PB2 n = 0,1 The Receiver front-end logic samples ...
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ATmega161(L) 72 Figure 46. Sampling Received Data Note: 1. This figure is not valid when the UART speed is doubled. See Transmission” on page 78 When the stop bit enters the Receiver, the majority of the three samples must be ...
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Multi-processor Communication Mode UART Control UART0 I/O Data Register – UDR0 UART1 I/O Data Register – UDR1 UART0 Control and Status Registers – UCSR0A 1228D–AVR–02/07 The Multi-processor Communication mode enables several Slave MCUs to receive data from a master MCU. ...
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UART1 Control and Status Registers – UCSR1A ATmega161(L) 74 Bit $02 ($22) RXC1 TXC1 UDRE1 Read/Write R R/W R Initial Value • Bit 7 RXC0/RXC1: UART Receive Complete – This bit is set (one) ...
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UART0 Control and Status Registers – UCSR0B UART1 Control and Status Registers – UCSR1B 1228D–AVR–02/07 • Bit 2 Res: Reserved Bit – This bit is reserved bit in the ATmega161 and will always read as zero. • Bit 1 U2X0/U2X1: ...
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Baud Rate Generator ATmega161(L) 76 • Bit 2 CHR90/CHR91: 9-bit Characters – When this bit is set (one), transmitted and received characters are nine bits long, plus start and stop bits. The ninth bit is read and written by using ...
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Table 24. UBR Settings at Various Crystal Frequencies Baud Rate 1 MHz %Error 1.8432 MHz %Error 2400 UBR= 25 0.2 UBR= 4800 UBR= 12 0.2 UBR= 9600 UBR= 6 7.5 UBR= 14400 UBR= 3 7.8 UBR= 19200 UBR= 2 ...
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UART0 and UART1 High Byte Baud Rate Register UBRRHI UART0 Baud Rate Register Low Byte – UBRR0 UART1 Baud Rate Register Low Byte – UBRR1 Double-speed Transmission ATmega161(L) 78 Bit $20 ($40) MSB1 Read/Write R/W R/W R/W ...
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The Baud Rate Generator in Double UART Speed Mode 1228D–AVR–02/07 Note that the baud rate equation is different from the equation on page 76 when the UART speed is doubled: BAUD • BAUD = Baud rate • Crystal ...
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Table 25. UBR Settings at Various Crystal Frequencies in Double-speed Mode Baud Rate 1.0000 MHz 2400 UBR = 51 4800 UBR = 25 9600 UBR = 12 14400 UBR = 8 19200 UBR = 6 28800 UBR = 3 38400 ...
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Analog Comparator Analog Comparator Control and Status Register – ACSR 1228D–AVR–02/07 The Analog Comparator compares the input values on the positive input PB2 (AIN0) and negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher ...
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ATmega161(L) 82 • Bit 4 ACI: Analog Comparator Interrupt Flag – This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE ...
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Internal Voltage Reference Voltage Reference Enable Signals and Start- up Time 1228D–AVR–02/07 ATmega161 features an internal voltage reference with a nominal voltage of 1.22V. This reference can be used as an input to the Analog Comparator. The voltage reference has ...
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Interface to External Memory MCU Control Register – MCUCR Extended MCU Control Register – EMCUCR ATmega161(L) 84 With all the features the external memory interface provides well suited to operate as an interface to memory devices such as ...
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Bits 3..2 EMCUCR – SRW01, SRW00: Wait State Select Bits for Lower Page The SRW01 and SRW00 bits control the number of wait states for the lower page of the external memory address space (see Table 27). (1) ...
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ATmega161(L) 86 Figure 49. External Memory with Page Select External Memory (0-63K x 8) Figure 50. External Data Memory Cycles without Wait State (SRWn1 = 0 and SRWn0 (1) =0) T1 System Clock Ø ALE Address [15..8] Prev. addr. XX ...
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Figure 51. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1 T1 System Clock Ø ALE Prev. addr. Address [15..8] XX Prev. data Data/Address [7..0] XX Address WR Prev. data Data/Address [7..0] Address XX RD Note: ...
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Using the External Memory Interface ATmega161(L) 88 The interface consists of: Port A: multiplexed low-order address bus and data bus Port C: high-order address bus The ALE pin: address latch enable The RD and WR pin: read and write strobes ...
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I/O Ports Port A Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port A as General Digital I/O 1228D–AVR–02/07 All AVR ports have true read-modify-write functionality when used ...
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Port A Schematics ATmega161(L) 90 Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 29. DDAn Effects on Port A Pins DDAn PORTAn I Input 0 1 Input ...
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Port B Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB 1228D–AVR–02/07 Port 8-bit bi-directional I/O port. Three I/O memory address locations are allocated for the ...
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Port B as General Digital I/O Alternate Functions of Port B ATmega161(L) 92 All eight pins in Port B have equal functionality when used as digital I/O pins. PBn, general I/O pin: The DDBn bit in the DDRB Register selects ...
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TXD1/AIN1 Port B, Bit 3 – AIN1, Analog Comparator Negative Input. This pin also serves as the negative input of the On-chip Analog Comparator. TXD1, Transmit Data (Data output pin for the UART1). When the UART1 Transmitter is ...
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Port B Schematics ATmega161(L) 94 Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 56. Port B Schematic Diagram (Pins PB0 and PB1) PBn WP: WRITE PORTB WD: WRITE DDRB RL: ...
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Figure 57. Port B Schematic Diagram (Pin PB2) MOS PULL- UP PB2 WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB RXD1: UART1 RECEIVE DATA RXEN1: UART1 RECEIVE ENABLE AIN0: ANALOG ...
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ATmega161(L) 96 Figure 59. Port B Schematic Diagram (Pin PB4) MOS PULL- UP PB4 WP: WRITE PORTB WRITE DDRB WD: RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB SPI MASTER ENABLE MSTR: SPE: SPI ENABLE Figure 60. ...
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Figure 61. Port B Schematic Diagram (Pin PB6) MOS PULL- UP PB6 WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB SPE: SPI ENABLE MASTER SELECT MSTR Figure 62. Port B ...
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Port C Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port C as General Digital I/O ATmega161(L) 98 Port 8-bit bi-directional I/O port. Three I/O ...
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Port C Schematics 1228D–AVR–02/07 Table 32. DDCn Effects on Port C Pins DDCn PORTCn I Input 0 1 Input 1 0 Output 1 1 Output Note 6,…0, pin number Note that all port pins are ...
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Port D Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port D as General Digital I/O ATmega161(L) 100 Port 8-bit bi-directional I/O port with internal ...
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Alternate Functions of Port D 1228D–AVR–02/07 has to be cleared (zero) or the pin has to be configured as an output pin. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not ...
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Port D Schematics ATmega161(L) 102 Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 64. Port D Schematic Diagram (Pin PD0) MOS PULL- UP PD0 WP: WRITE PORTD WD: WRITE DDRD ...
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Figure 66. Port D Schematic Diagram (Pins PD2 and PD3) WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD Figure 67. Port D Schematic Diagram ...
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ATmega161(L) 104 Figure 68. Port D Schematic Diagram (Pin PD5) WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD AS2 ASYNCH SELECT T/C2 Figure 69. Port D Schematic Diagram (Pin PD6) WP: ...
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Figure 70. Port D Schematic Diagram (Pin PD7) WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD RE: READ ENABLE SRE: EXTERNAL SRAM ENABLE ATmega161(L) 105 ...
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Port E Port E Data Register – PORTE Port E Data Direction Register – DDRE Port E Input Pins Address – PINE Port E as General Digital I/O ATmega161(L) 106 Port 3-bit bi-directional I/O port with internal ...
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Alternate Functions of Port E 1228D–AVR–02/07 Table 36. DDEn Bits on Port E Pins DDEn PORTEn I Input 0 1 Input 1 0 Output 1 1 Output Note 2,1,0, pin number. The alternate pin configuration is ...
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Port E Schematics ATmega161(L) 108 Figure 71. Port E Schematic Diagram (Pin PE0) MOS PULL- UP PE0 WP: WRITE PORTE WD: WRITE DDRE RL: READ PORTE LATCH RP: READ PORTE PIN RD: READ DDRE ACIC: COMPARATOR IC ENABLE ACO: COMPARATOR ...
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Figure 73. Port E Schematic Diagram (Pin PE2) PE2 WP: WRITE PORTE WD: WRITE DDRE RL: READ PORTE LATCH RP: READ PORTE PIN RD: READ DDRE ATmega161(L) DDE2 PORTE2 COM1B0 COM1B1 COMP. MATCH 1B PWM10 PWM11 FOC1B 109 ...
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Memory Programming Boot Loader Support ATmega161(L) 110 The ATmega161 provides a mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates, controlled by the MCU using a Flash-resident Boot Loader program. The ...
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Entering the Boot Loader Program 1228D–AVR–02/07 • Protect the entire Flash from a software update by the Boot Loader program • Only protect the Boot Loader section from a software update by the Boot Loader program • Only protect the ...
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Capabilities of the Boot Loader Self-programming the Flash Setting the Boot Loader Lock bits by SPM Performing Page Erase by SPM ATmega161(L) 112 Table 39. Boot Reset Fuse, BOOTRST BOOTRST Reset Address 1 Reset Vector = Application Reset (address $0000) ...
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Fill the Temporary Buffer Perform a Page Write Addressing the FLASH during Self-programming 1228D–AVR–02/07 To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write “0001” to SPMCR, and execute SPM within four clock ...
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Store Program Memory Control Register – SPMCR ATmega161(L) 114 The Store Program Memory Control Register contains the control bits needed to control the programming of the Flash from internal code execution. Bit $37 ($57) – – Read/Write ...
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EEPROM Write Prevents Writing to SPMCR Reading the Fuse and Lock bits from Software 1228D–AVR–02/07 Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuse and Lock bits from software will also be prevented ...
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Program Memory Lock bits Fuse bits ATmega161(L) 116 The ATmega161 MCU provides six Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 40. The Lock bits can only ...
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... Programming mode. An auto-erase cycle is provided with the self-timed EEPROM programming operation in the Serial Programming mode. During programming, the supply voltage must be in accordance with Table 41. Table 41. Supply Voltage during Programming Part Serial Programming ATmega161L 2.7 - 5.5V ATmega161 4.0 - 5.5V ATmega161(L) (3) ,” ...
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Parallel Programming Signal Names ATmega161(L) 118 This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the ATmega161. Pulses are assumed least 500 ns unless otherwise ...
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Enter Programming Mode Chip Erase 1228D–AVR–02/07 Table 42. Pin Name Mapping Signal Name in Programming Mode Pin Name PAGEL PD7 BS2 PA0 DATA PB7 - 0 Table 43. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 ...
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Programming the Flash ATmega161(L) 120 The Flash is organized as 128 pages of 128 bytes each. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. ...
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Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSYgoes low. 2. Wait until RDY/BSY goes high. (See Figure 77 for signal waveforms.) J. End Page Programming 1. Set XA1, XA0 to “10”. ...
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Programming the EEPROM ATmega161(L) 122 The programming algorithm for the EEPROM Data memory is as follows (refer to “Pro- gramming the Flash” for details on command, address and data loading Load Command “0001 0001” Load Address ...
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Reading the Flash Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits 1228D–AVR–02/07 The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 120 for details on command and address loading): ...
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Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics ATmega161(L) 124 The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 120 for details on command loading): ...
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Serial Downloading 1228D–AVR–02/07 Table 45. Parallel Programming Characteristics, T (1)(2)(3) 10% Symbol Parameter V Programming Enable Voltage PP I Programming Enable Current PP t Data and Control Valid before XTAL1 High DVXH t XTAL1 Pulse Width High XHXL t Data ...
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Serial Programming Algorithm Data Polling Flash ATmega161(L) 126 When writing serial data to the ATmega161, data is clocked on the rising edge of SCK. When reading data from the ATmega161, data is clocked on the falling edge of SCK. See ...
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Data Polling EEPROM 1228D–AVR–02/07 t before programming the next page chip-erased device contains $FF in WD_FLASH all locations, programming of addresses that are meant to contain $FF can be skipped. See Table 46 for t value. WD_FLASH When ...
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Table 48. Serial Programming Instruction Set Instruction Byte 1 Programming Enable 1010 1100 Chip Erase 1010 1100 Read Program Memory 0010 H000 Load Program Memory 0100 H000 Page Write Program Memory 0100 1100 Page Read EEPROM Memory 1010 0000 Write ...
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Serial Programming Characteristics 1228D–AVR–02/07 Figure 81. Serial Programming Timing MOSI t OVSH SCK MISO Table 49. Serial Programming Characteristics, T (unless otherwise noted) Symbol Parameter 1/t Oscillator Frequency CLCL t Oscillator Period CLCL t SCK Pulse Width High SHSL t ...
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Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin except RESET with Respect to Ground .............................-1. Voltage on RESET with Respect to Ground ....-1.0V to +13.0V Maximum ...
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DC Characteristics T = -40°C to 85° 2.7V to 5.5V (unless otherwise noted Symbol Parameter V Input Low Voltage IL V Input Low Voltage IL1 V Input High Voltage IH V Input High Voltage IH1 V ...
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If I exceeds the test condition greater than the listed test condition. 5. Minimum V for power-down is 2V. CC External Clock Drive Waveforms ATmega161(L) 132 may exceed the related specification. Pins are not guaranteed to source current ...
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External Data Memory Timing Table 51. External Data Memory Characteristics, 4.0 - 5.5 Volts, No Wait State Symbol Parameter 0 1/t Oscillator Frequency CLCL 1 t ALE Pulse Width LHLL 2 t Address Valid A to ALE Low AVLL Address ...
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Table 53. External Data Memory Characteristics, 4.0 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0 Symbol Parameter 0 1/t Oscillator Frequency CLCL 10 t Read Low to Data Valid RLDV Pulse Width RLRH 15 t Data ...
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Table 55. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait State (Continued) Symbol Parameter Pulse Width RLRH 13 t Data Setup to WR Low DVWL 14 t Data Hold After WR High WHDX 15 t ...
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ATmega161(L) 136 Figure 83. External Memory Timing (SRWn1 = 0, SRWn0 = 0) T1 System Clock Ø ALE Prev. addr. XX Address [15..8] Prev. data Data/Address [7.. Prev. data Data/Address [7.. Figure 84. External Memory Timing ...
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Figure 85. External Memory Timing (SRWn1 = 1, SRWn0 = System Clock Ø 1 ALE 4 Address [15..8] Prev. addr Data/Address [7..0] Prev. data XX Address 6 WR Data/Address [7..0] Address Prev. data XX ...
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Typical Characteristics ATmega161(L) 138 Analog Comparator offset voltage is measured as absolute offset. Figure 87. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE ...
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Figure 89. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT -10 0 0.5 1 1.5 2 Figure 90. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 1400 ...
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ATmega161(L) 140 Figure 91. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 120 T = 25˚C A 100 T = 85˚ 0.5 1 1.5 Figure 92. Pull-up Resistor Current ...
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Figure 93. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 Figure 94. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT ...
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ATmega161(L) 142 Figure 95. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 Figure 96. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. ...
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Figure 97. I/O Pin Input Threshold vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 1 0.5 0 2.7 Figure 98. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 0.14 ...
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Register Summary Address Name Bit 7 $3F ($5F) SREG I $3E ($5E) SPH SP15 $3D ($5D) SPL SP7 Reserved $3C ($5C) $3B ($5B) GIMSK INT1 $3A ($5A) GIFR INTF1 $39 ($59) TIMSK TOIE1 $38 ($58) TIFR TOV1 $37 ($57) SPMCR ...
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Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the Status Flags are cleared by writing a logical “1” to them. Note ...
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Instruction Set Summary Mnemonic Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers ADIW Rdl, K Add Immediate to Word SUB Rd, Rr Subtract Two Registers SUBI Rd, K ...
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Instruction Set Summary (Continued) Mnemonic Operands Description BRTS k Branch if T-flag Set BRTC k Branch if T-flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt ...
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Instruction Set Summary (Continued) Mnemonic Operands Description SEZ Set Zero Flag CLZ Clear Zero Flag SEI Global Interrupt Enable CLI Global Interrupt Disable SES Set Signed Test Flag CLS Clear Signed Test Flag SEV Set Two’s Complement Overflow CLV Clear ...
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... Note: This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 44A 44-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 1228D– ...
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Packaging Information 44A PIN 0˚~7˚ Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 ...
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PIN 0˚~7˚ Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum ...
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Errata ATmega161 Rev. E ATmega161(L) 152 • PWM not Phase Correct • Increased Interrupt Latency • Interrupt Return Fails when Stack Pointer Addresses the External Memory • Writing UBBRH Affects both UART0 and UART1 • Store Program Memory Instruction May ...
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Store Program Memory Instruction May Fail At certain frequencies and voltages, the store program memory (SPM) instruction may fail. Problem Fix/Workaround Avoid using the SPM instruction. ATmega161(L) 153 ...
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Data Sheet Change Log for ATmega161 Changes from Rev. 1228C-08/02 to Rev. 1228D-02/07 Changes from Rev. 1228B-09/01 to Rev. 1228C-08/02 ATmega161(L) 154 This document contains a log on the changes made to the data sheet for ATmega161. 1 Package Drawing ...
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Table of Contents 1228D–AVR–02/07 Features................................................................................................. 1 Disclaimer.............................................................................................. 1 Pin Configuration.................................................................................. 2 Description ............................................................................................ 3 Block Diagram ...................................................................................................... 4 Pin Descriptions.................................................................................................... 5 Crystal Oscillator................................................................................................... 6 Architectural Overview......................................................................... 7 The General Purpose Register File .................................................................... 10 ALU – Arithmetic Logic Unit................................................................................ 11 ...
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ATmega161(L) ii Internal Voltage Reference ................................................................ 83 Voltage Reference Enable Signals and Start-up Time ....................................... 83 Interface to External Memory ............................................................ 84 Using the External Memory Interface ................................................................. 88 I/O Ports............................................................................................... 89 Port A.................................................................................................................. 89 Port B.................................................................................................................. 91 Port B ...
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Errata ................................................................................................. 152 ATmega161 Rev. E .......................................................................................... 152 Data Sheet Change Log for ATmega161 ........................................ 154 Changes from Rev. 1228B-09/01 to Rev. 1228C-08/02 ................................... 154 Table of Contents .................................................................................. i ATmega161(L) iii ...
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ATmega161(L) iv 1228D–AVR–02/07 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...