ATMEGA161L-4PI Atmel, ATMEGA161L-4PI Datasheet - Page 84

• Manufacturer Part Number: ATMEGA161L-4PI
• Description: IC AVR MCU 16K LV 4MHZ IND 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161L-4PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Interface to External
Memory
MCU Control Register –
MCUCR
Extended MCU Control
Register – EMCUCR
84
ATmega161(L)
With all the features the external memory interface provides, it is well suited to operate
as an interface to memory devices such as external SRAM and Flash, and peripherals
such as LCD display, A/D, D/A, etc. The control bits for the external memory interface
are located in two registers, the MCU Control Register (MCUCR) and the Extended
MCU Control Register (EMCUCR).
• Bit 7 MCUCR – SRE: External SRAM Enable
When the SRE bit is set (one), the external memory interface is enabled and the pin
functions AD0 - 7 (Port A), A8 - 15 (Port C), ALE (Port E), WR and RD (Port D) are acti-
vated as the alternate pin functions. The SRE bit overrides any pin direction settings in
the respective Data Direction Registers. See Figure 50 through Figure 53 for a descrip-
tion of the external memory pin functions. When the SRE bit is cleared (zero), the
external Data memory interface is disabled and the normal pin and data direction set-
tings are used
• Bits 6..4 EMCUCR – SRL2, SRL1, SRL0: Wait State Page Limit
It is possible to configure different wait states for different external memory addresses.
The external memory address space can be divided into two pages with different wait
state bits. The SRL2, SRL1 and SRL0 bits select the split of the pages (see Table 28
and Figure 49). As defaults, the SRL2, SRL1 and SRL0 bits are set to zero and the
entire external memory address space is treated as one page. When the entire SRAM
address space is configured as one page, the wait states are configured by the SRW11
and SRW10 bits.
• Bit 1 EMCUCR and Bit 6 MCUCR – SRW11, SRW10: Wait State Select Bits for
The SRW11 and SRW10 bits control the number of wait states for the upper page of the
external memory address space (see Table 27). Note that if the SRL2, SRL1, and SRL0
bits are set to zero, the SRW11 and SRW10 bit settings will define the wait state of the
entire SRAM address space.
Bit
$35 ($55)
Read/Write
Initial Value
Bit
$36 ($56)
Read/Write
Initial Value
Upper Page
SM0
R/W
SRE
R/W
7
0
7
0
SRW10
SRL2
R/W
R/W
6
0
6
0
SRL1
R/W
R/W
SE
5
0
5
0
SRL0
R/W
SM1
R/W
4
0
4
0
SRW01
ISC11
R/W
R/W
3
0
3
0
SRW00
R/W
ISC10
R/W
2
0
2
0
SRW11
R/W
ISC01
R/W
1
0
1
0
ISC20
R/W
ISC00
R/W
0
0
1228D–AVR–02/07
0
0
EMCUCR
MCUCR