PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 273
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18C858-E/L
Manufacturer Part Number
PIC18C858-E/L
Description
IC MCU OTP 16KX16 CAN 84PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C858-E/L
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
84-PLCC
For Use With
AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC18C858E/L
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C858-E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 273 of 366
- Download datasheet (7Mb)
BRA
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
2000 Microchip Technology Inc.
Before Instruction
After Instruction
operation
Decode
No
PC
PC
Q1
Read literal
operation
Unconditional Branch
[ label ] BRA
-1024
(PC) + 2 + 2n
None
Add the 2’s complement number
’2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a two-
cycle instruction.
1
2
HERE
1101
No
Q2
’n’
=
=
address (HERE)
address (Jump)
n
0nnn
BRA
operation
1023
Process
Data
No
Q3
n
PC
Jump
nnnn
Advanced Information
Write to PC
operation
No
Q4
nnnn
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
FLAG_REG
FLAG_REG
Q1
register ’f’
Bit Set f
[ label ] BSF
0
0
a
1
None
Bit 'b' in register 'f' is set. If ’a’ is 0
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value (default).
1
1
BSF
Read
1000
Q2
=
=
f
b
[0,1]
f<b>
PIC18CXX8
255
7
0x0A
0x8A
FLAG_REG, 7, 1
bbba
Process
Data
Q3
f, b [,a]
DS30475A-page 273
ffff
register ’f’
Write
Q4
ffff
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