PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 95

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

8.4
PORTD is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (=1) will make the corresponding PORTD pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISD bit (=0) will
make the corresponding PORTD pin an output (i.e., put
the contents of the output latch on the selected pin).
Read-modify-write operations on the LATD register
reads and writes the latched output value for PORTD.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
PORTD can be configured as an 8-bit wide micro-
processor port (parallel slave port), by setting control
bit PSPMODE (PSPCON register). In this mode, the
input buffers are TTL. See Section 9.0 for additional
information on the Parallel Slave Port (PSP).
EXAMPLE 8-4:
 2000 Microchip Technology Inc.
CLRF
CLRF
MOVLW
MOVWF
PORTD, TRISD and LATD Registers
PORTD
LATD
0xCF
TRISD
INITIALIZING PORTD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD3:RD0 as inputs
; RD5:RD4 as outputs
; RD7:RD6 as inputs
Advanced Information
FIGURE 8-7:
WR TRISD
WR LATD
or
WR PORTD
Note: I/O pins have diode protection to V
Data
Bus
RD PORTD
TRIS Latch
Data Latch
D
D
CK
CK
PORTD BLOCK DIAGRAM
IN I/O PORT MODE
RD LATD
RD TRISD
Q
Q
PIC18CXX8
Q
EN
EN
DD
D
DS30475A-page 95
Schmitt
Trigger
Input
Buffer
and V
SS
.
I/O Pin