PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 274
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18C858-E/L
Manufacturer Part Number
PIC18C858-E/L
Description
IC MCU OTP 16KX16 CAN 84PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C858-E/L
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
84-PLCC
For Use With
AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC18C858E/L
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C858-E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 274 of 366
- Download datasheet (7Mb)
PIC18CXX8
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Example:
DS30475A-page 274
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
No
No
No
Q1
Q1
Q1
PC
PC
Bit Test File, Skip if Clear
[ label ] BTFSC f, b [,a]
0
0
a
skip if (f<b>) = 0
None
If bit 'b' in register ’f' is 0, then the
next instruction is skipped.
If bit 'b' is 0, then the next instruction
fetched during the current instruction
execution is discarded, and a NOP is
executed instead, making this a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the BSR
value.
1
1(2)
Note: 3 cycles if skip and followed
HERE
FALSE
TRUE
register ’f’
operation
operation
operation
Read
1011
No
No
No
Q2
Q2
Q2
=
=
=
=
=
f
b
[0,1]
by a 2-word instruction.
255
7
address (HERE)
0;
address (TRUE)
1;
address (FALSE)
BTFSC
:
:
bbba
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
FLAG, 1, ACCESS
ffff
Advanced Information
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Example:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
No
No
No
Q1
Q1
Q1
PC
PC
Bit Test File, Skip if Set
[ label ] BTFSS f, b [,a]
0
0
a
skip if (f<b>) = 1
None
If bit 'b' in register 'f' is 1 then the next
instruction is skipped.
If bit 'b' is 1, then the next instruction
fetched during the current instruc-
tion execution, is discarded and an
NOP is executed instead, making this
a two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the BSR
value.
1
1(2)
Note: 3 cycles if skip and followed
register ’f’
HERE
FALSE
TRUE
operation
operation
operation
Read
1010
No
No
No
Q2
Q2
Q2
=
=
=
=
=
f
b < 7
[0,1]
by a 2-word instruction.
2000 Microchip Technology Inc.
255
address (HERE)
0;
address (FALSE)
1;
address (TRUE)
BTFSS
:
:
bbba
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
FLAG, 1, ACCESS
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
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