PIC18C452-E/PT Microchip Technology, PIC18C452-E/PT Datasheet - Page 100
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PIC18C452-E/PT
Manufacturer Part Number
PIC18C452-E/PT
Description
IC MCU OTP 16KX16 A/D 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C242-ISO.pdf
(305 pages)
4.PIC18C242-ISO.pdf
(12 pages)
Specifications of PIC18C452-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC18C452E/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C452-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C242-ISO PDF datasheet #3
- PIC18C242-ISO PDF datasheet #4
- Current page: 100 of 305
- Download datasheet (6Mb)
PIC18CXX2
10.1
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
FIGURE 10-1:
FIGURE 10-2:
DS39206C-page 98
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T13CKI/T1OSO
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T1CKI/T1OSO
Timer1 Operation
T1OSI
TMR1IF
Overflow
Interrupt
Flag bit
TMR1IF
Overflow
Interrupt
Flag bit
Data Bus<7:0>
Write TMR1L
Read TMR1L
T1OSI
TIMER1 BLOCK DIAGRAM
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
8
T1OSC
TMR1H
High Byte
TMR1H
T1OSC
Timer 1
8
8
TMR1
T1OSCEN
Enable
Oscillator
TMR1
Oscillator
Enable
T1OSCEN
TMR1L
TMR1L
CLR
8
(1)
(1)
CLR
Clock
Internal
F
OSC
/4
TMR1ON
CCP Special Event Trigger
Clock
Internal
F
On/Off
OSC
TMR1CS
/4
1
0
TMR1ON
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 13.0).
CCP Special Event Trigger
On/Off
TMR1CS
T1CKPS1:T1CKPS0
1
0
T1SYNC
Prescaler
1, 2, 4, 8
T1CKPS1:T1CKPS0
0
1
T1SYNC
Prescaler
1, 2, 4, 8
2
0
1
2
Synchronized
2001 Microchip Technology Inc.
Clock Input
Synchronize
SLEEP Input
Synchronized
Clock Input
det
Synchronize
SLEEP Input
det
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