PIC17C766-33E/L Microchip Technology, PIC17C766-33E/L Datasheet - Page 150
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC17C766-33E/L
Manufacturer Part Number
PIC17C766-33E/L
Description
IC MCU CMOS 33MHZ 16K EPRM84PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C766-33E/L
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
66
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
84-PLCC
For Use With
AC164318 - MODULE SKT MPLAB PM3 84PLCCDVA17XL841 - DEVICE ADAPTER FOR PIC17C762DM173001 - KIT DEVELOPMENT PICDEM17AC164027 - ADAPTER PICSTART PLUS 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C766-33E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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- Download datasheet (6Mb)
PIC17C7XX
15.2.3
While in SLEEP mode, the I
addresses or data and when an address match or com-
plete byte transfer occurs, wake the processor from
SLEEP (if the SSP interrupt is enabled).
TABLE 15-3:
DS30289B-page 150
07h, Unbanked INTSTA
10h, Bank 4
11h, Bank 4
10h. Bank 6
14h, Bank 6
11h, Bank 6
12h, Bank 6
13h, Bank 6
Legend:
Address
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in I
SLEEP OPERATION
PIR2
PIE2
SSPADD
SSPBUF
SSPCON1
SSPCON2
SSPSTAT
Name
REGISTERS ASSOCIATED WITH I
Synchronous Serial Port (I
Synchronous Serial Port Receive Buffer/Transmit Register
SSPIE
WCOL
SSPIF
GCEN
Bit 7
PEIF
SMP
2
C module can receive
ACKSTAT
T0CKIF
SSPOV
BCLIF
BCLIE
Bit 6
CKE
SSPEN
ACKDT
ADIE
Bit 5
ADIF
T0IF
D/A
2
C mode) Address Register
ACKEN
INTF
Bit 4
CKP
—
—
P
2
C OPERATION
SSPM3
CA4IF
CA4IE
RCEN
PEIE
Bit 3
S
15.2.4
A RESET disables the SSP module and terminates the
current transfer.
T0CKIE
SSPM2
CA3IF
CA3IE
Bit 2
PEN
R/W
EFFECTS OF A RESET
SSPM1
TX2IE
RSEN
TX2IF
Bit 1
T0IE
UA
SSPM0
RC2IE
RC2IF
INTE
Bit 0
SEN
BF
2000 Microchip Technology Inc.
2
C mode.
0000 0000
000- 0000
000- 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
POR, BOR
MCLR, WDT
0000 0000
000- 0000
000- 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
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