ATMEGA128-16MI Atmel, ATMEGA128-16MI Datasheet - Page 174
ATMEGA128-16MI
Manufacturer Part Number
ATMEGA128-16MI
Description
IC AVR MCU 128K 16MHZ IND 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
ATMEGA128-16MI
Manufacturer:
ATMEL
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External Clock
Synchronous Clock
Operation
174
ATmega128
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
External clock input from the XCK pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the transmitter and receiver. This process introduces
a two CPU clock period delay and therefore the maximum external XCK clock frequency is lim-
ited by the following equation:
Note that f
add some margin to avoid possible loss of data due to frequency variations.
When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input
(slave) or clock output (master). The dependency between the clock edges and data sampling or
data change is the same. The basic principle is that data input (on RxD) is sampled at the oppo-
site XCK clock edge of the edge the data output (TxD) is changed.
Figure 81. Synchronous Mode XCK Timing.
The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is
used for data change. As
ing XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at
falling XCK edge and sampled at rising XCK edge.
UCPOL = 1
UCPOL = 0
osc
depends on the stability of the system clock source. It is therefore recommended to
Figure 80
RxD / TxD
RxD / TxD
XCK
XCK
Figure 81
for details.
shows, when UCPOL is zero the data will be changed at ris-
f
XCK
<
f
---------- -
OSC
4
Sample
Sample
2467V–AVR–02/11
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