ATMEGA32-16PI Atmel, ATMEGA32-16PI Datasheet - Page 120
![IC AVR MCU 32K 16MHZ IND 40-DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA32-16PI
Manufacturer Part Number
ATMEGA32-16PI
Description
IC AVR MCU 32K 16MHZ IND 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32-16PI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA32-16PI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Fast PWM Mode
2503Q–AVR–02/11
pin is set to output. The waveform generated will have a maximum frequency of f
when OCR2 is set to zero (0x00). The waveform frequency is defined by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the
counter counts from MAX to 0x00.
The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM option by its sin-
gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In
non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the compare
match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the
output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the
operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in
gram for illustrating the single-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare
matches between OCR2 and TCNT2.
Figure 58. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Set-
ting the COM21:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can
be generated by setting the COM21:0 to 3 (see
will only be visible on the port pin if the data direction for the port pin is set as output. The PWM
waveform is generated by setting (or clearing) the OC2 Register at the compare match between
TCNTn
OCn
OCn
Period
1
Figure
2
58. The TCNT2 value is in the timing diagram shown as a histo-
3
f
TOV2
OCn
) is set each time the counter reaches MAX. If the inter-
=
4
TOV2
---------------------------------------------- -
2 N
⋅
Flag is set in the same timer clock cycle that the
⋅
5
f
Table 52 on page
(
clk_I/O
1
+
OCRn
6
)
7
126). The actual OC2 value
ATmega32(L)
OCRn Interrupt Flag Set
OCRn Update and
TOVn Interrupt Flag Set
(COMn1:0 = 2)
(COMn1:0 = 3)
OC2
= f
clk_I/O
120
/2
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