ATMEGA8515L-8PC Atmel, ATMEGA8515L-8PC Datasheet - Page 115
![IC AVR MCU 8K LV 8MHZ COM 40-DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA8515L-8PC
Manufacturer Part Number
ATMEGA8515L-8PC
Description
IC AVR MCU 8K LV 8MHZ COM 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8515L-8PC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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Phase and Frequency Correct
PWM Mode
2512K–AVR–01/10
The phase and frequency correct Pulse Width Modulation, or phase and frequency cor-
rect PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency
correct PWM waveform generation option. The phase and frequency correct PWM
mode is, like the phase correct PWM mode, based on a dual-slope operation. The coun-
ter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM.
In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the
Compare Match between TCNT1 and OCR1x while upcounting, and set on the Com-
pare Match while downcounting. In inverting Compare Output mode, the operation is
inverted. The dual-slope operation gives a lower maximum operation frequency com-
pared to the single-slope operation. However, due to the symmetric feature of the dual-
slope PWM modes, these modes are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct
PWM mode is the time the OCR1x Register is updated by the OCR1x Buffer Register,
(see Figure 54 and Figure 55).
The PWM resolution for the phase and frequency correct PWM mode can be defined by
either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to
0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM
resolution in bits can be calculated using the following equation:
In phase and frequency correct PWM mode the counter is incremented until the counter
value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A
(WGM13:0 = 9). The counter has then reached the TOP and changes the count direc-
tion. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing
diagram for the phase correct and frequency correct PWM mode is shown on Figure 55.
The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is
used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for
illustrating the dual-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNT1 slopes represent Compare
Matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Com-
pare Match occurs.
Figure 55. Phase and Frequency Correct PWM Mode, Timing Diagram
TCNTn
OCnx
OCnx
Period
1
R
2
PFCPWM
=
3
log
---------------------------------- -
(
log
TOP
2 ( )
+
4
1
)
ATmega8515(L)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
OCRnx/TOP Update and
TOVn Interrupt Flag Set
(Interrupt on Bottom)
(COMnx1:0 = 2)
(COMnx1:0 = 3)
115
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