ATMEGA162V-1MC Atmel, ATMEGA162V-1MC Datasheet - Page 51
![IC MCU AVR 16K 1.8V 8MHZ 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA162V-1MC
Manufacturer Part Number
ATMEGA162V-1MC
Description
IC MCU AVR 16K 1.8V 8MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA162V-1MC
Core Processor
AVR
Core Size
8-Bit
Speed
1MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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Watchdog Timer Control
Register – WDTCR
2513C–AVR–09/02
shown in Table 22. Safety level 0 corresponds to the setting in ATmega161. There is no
restriction on enabling the WDT in any of the safety levels. Refer to “Timed Sequences
for Changing the Configuration of the Watchdog Timer” on page 54 for details.
Table 22. WDT Configuration as a Function of the Fuse Settings of M161C and
WDTON.
Figure 27. Watchdog Timer
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega162 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog
will not be disabled. Once written to one, hardware will clear this bit after four clock
cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In
Safety Levels 1 and 2, this bit must also be set when changing the prescaler bits. See
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 54.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is
written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared
Bit
Read/Write
Initial Value
M161C
Unprogrammed
Unprogrammed
Programmed
Programmed
R
7
–
0
WDTON
Unprogrammed
Programmed
Unprogrammed
Programmed
R
6
–
0
OSCILLATOR
WATCHDOG
R
5
–
0
Safety
Level
1
2
0
2
WDCE
R/W
4
0
WDT
Initial
State
Disabled
Enabled
Disabled
Enabled
WDE
R/W
3
0
ATmega162(V/U/L)
How to Disable
the WDT
Timed sequence
Always enabled
Timed sequence
Always enabled
WDP2
R/W
2
0
WDP1
R/W
1
0
WDP0
R/W
How to
Change Time-
out
Timed
sequence
Timed
sequence
No restriction
Timed
sequence
0
0
WDTCR
51
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