ATMEGA162V-1MC Atmel, ATMEGA162V-1MC Datasheet - Page 84
![IC MCU AVR 16K 1.8V 8MHZ 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA162V-1MC
Manufacturer Part Number
ATMEGA162V-1MC
Description
IC MCU AVR 16K 1.8V 8MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA162V-1MC
Core Processor
AVR
Core Size
8-Bit
Speed
1MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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General Interrupt Control
Register – GICR
84
ATmega162(V/U/L)
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity
on the pin will cause an interrupt request even if INT1 is configured as an output. The
corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Inter-
rupt Vector.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity
on the pin will cause an interrupt request even if INT0 is configured as an output. The
corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Inter-
rupt Vector.
• Bit 5 – INT2: External Interrupt Request 2 Enable
When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control2 bit (ISC2) in the
Extended MCU Control Register (EMCUCR) defines whether the external interrupt is
activated on rising or falling edge of the INT2 pin. Activity on the pin will cause an inter-
rupt request even if INT2 is configured as an output. The corresponding interrupt of
External Interrupt Request 2 is executed from the INT2 Interrupt Vector.
• Bit 4 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-
cuted from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the
PCMSK1 Register.
• Bit 3 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0
Register.
Bit
Read/Write
Initial Value
INT1
R/W
7
0
INT0
R/W
6
0
INT2
R/W
5
0
PCIE1
R/W
4
0
PCIE0
R/W
3
0
R
2
–
0
IVSEL
R/W
1
0
IVCE
R/W
2513C–AVR–09/02
0
0
GICR
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