PIC18F4439-E/PT Microchip Technology, PIC18F4439-E/PT Datasheet - Page 19
![IC PIC MCU FLASH 6KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F4439-E/PT
Manufacturer Part Number
PIC18F4439-E/PT
Description
IC PIC MCU FLASH 6KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2439-ISO.pdf
(322 pages)
3.PIC18F2439-ISO.pdf
(6 pages)
4.PIC18F2439-ISO.pdf
(34 pages)
Specifications of PIC18F4439-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
12KB (6K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
640 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
640 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4439-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
3.6
The Boot Block segment is programmed in exactly the
same manner as the ID locations (see Section 3.5).
Multi-panel writes must be disabled so that only
addresses in the range 0000h to 01FFh will be written.
The code sequence detailed in Table 3-7 should be
used, except that the address data used in “Step 3” will
be in the range 000000h to 0001FFh.
TABLE 3-8:
FIGURE 3-10:
2010 Microchip Technology Inc.
Step 1: Configure device for single panel writes.
Step 2: Direct access to configuration memory.
Step 3: Set Table Pointer for configuration word to be written. Write even/odd addresses.
4-bit Command
0000
0000
0000
0000
0000
0000
1100
0000
0000
0000
0000
0000
0000
0000
0000
1111
0000
0000
1111
0000
Boot Block Programming
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 00
8E A6
8C A6
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB ignored>
00 00
2A F6
<LSB ignored><MSB>
00 00
SET ADDRESS POINTER TO CONFIGURATION LOCATION
CONFIGURATION PROGRAMMING FLOW
Data Payload
Delay P9 Time
Configuration
Load Even
for Write
Program
Address
Done
Start
LSB
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 00h to 3C0006h to enable single panel writes.
BSF EECON1, EEPGD
BSF EECON1, CFGS
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming
NOP - hold SCLK high for time P9
INCF TBLPTRL
Load 2 bytes and start programming
NOP - hold SCLK high for time P9
Preliminary
3.7
Unlike code memory, the configuration bits are
programmed a byte at a time. The “Table Write, Begin
Programming” 4-bit command (1111) is used, but only
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses,
and the MSB will be written to odd addresses. The
code
configuration locations is shown in Figure 3-8.
sequence
Core Instruction
Configuration Bits Programming
Delay P9 Time
Configuration
Load Odd
for Write
Program
Address
Done
Start
MSB
to
PIC18FXX39
program
two
DS30480C-page 19
consecutive