PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet - Page 90

• Manufacturer Part Number: PIC18F4431-E/ML
• Description: IC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
8.4
The minimum erase block is 32 words or 64 bytes.
Larger blocks of program memory can be bulk erased
only through the use of an external programmer or
ICSP control. Word erase in the Flash array is not
supported.
When initiating an erase sequence from the micro-
controller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased;
TBLPTR<5:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit (EECON1<7>) must be set to point to
the
(EECON1<2>) must be set to enable write operations.
The FREE bit (EECON1<4>) is set to select an erase
operation.
For protection, the write initiate sequence using
EECON2 must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 8-2:
DS39616D-page 90
Flash
Required
Sequence
Erasing Flash Program Memory
ERASE_ROW
program
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
memory.
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON2, WR
INTCON, GIE
The
WREN
bit
; load TBLPTR with the base
; address of the memory block
; point to Flash program memory
; access Flash program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
; write 55H
; write 0AAH
; start erase (CPU stall)
; re-enable interrupts
8.4.1
The sequence of events for erasing a block of internal
program memory location is:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Load the Table Pointer with the address of the
row being erased.
Set the EECON1 register for the erase
operation:
- set the EEPGD bit to point to program memory;
- clear the CFGS bit to access program memory;
- set the WREN bit to enable writes;
- set the FREE bit to enable the erase.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit. This will begin the row erase
cycle.
The CPU will stall for the duration of the erase
(about 2 ms using internal timer).
Execute a NOP.
Re-enable interrupts.
FLASH PROGRAM MEMORY
ERASE SEQUENCE
 2010 Microchip Technology Inc.