PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet - Page 30

• Manufacturer Part Number: PIC18F4431-E/ML
• Description: IC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
TABLE 5-4:
DS30500B-page 30
MCLRE
EXCLKMX
PWM4MX
SSPMX
FLTAMX
BKBUG
LVP
STVREN
CP3
CP2
CP1
CP0
Note 1:
Bit Name
(5)
(5)
2:
3:
4:
5:
(4)
(4)
(4)
(4)
Polarity control bits HPOL and LPOL define PWM signal output active and inactive states, PWM states
generated by the fault inputs or PWM manual override.
PWM6 and PWM7 output channels are only available on the PIC18F4X21 devices.
When PWMPIN = 0, PWMEN<2:0> = 101 if device has eight PWM output pins (40 and 44-pin devices)
and PWMEN<2:0> = 100 if the device has six PWM output pins (28-pin device). PWM output polarity is
defined by HPOL and LPOL.
This bit is reserved on PIC18F2X31 devices and should be maintained set (i.e., equal to ‘1’).
For PIC18FX431 devices only.
PIC18FXX31 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Configuration
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG4L
CONFIG4L
CONFIG4L
CONFIG5L
CONFIG5L
CONFIG5L
CONFIG5L
Words
1 = MCLR pin enabled; RE3 input pin disabled
0 = RE3 input pin enabled; MCLR disabled
1 = TMR0/T5CKI external clock input is multiplexed with RC3
0 = TMR0/T5CKI external clock input is multiplexed with RD0
PWM4 Mux bit
1 = PWM4 output is multiplexed with RB5
0 = PWM4 output is multiplexed with RD5
SSP I/O Mux bit
1 = SCK/SCL clocks and SDA/SDI data are multiplexed with RC5 and RC4,
0 = SCK/SCL clocks and SDA/SDI data are multiplexed with RD3 and RD2,
1 = FLTA input is multiplexed with RC1
0 = FLTA input is multiplexed with RD4
Background Debugger Enable bit
1 = Background debugger disabled (RB6,RB7 have I/O port function)
0 = Background debugger functions enabled (RB6, RB7 have ICSP serial
Low Voltage Programming Enable bit
1 = Low voltage programming enabled
0 = Low voltage programming disabled
1 = RESET on stack overflow/underflow enabled
0 = RESET on stack overflow/underflow disabled
Code Protection bit
1 = Block 3 (003000h-003FFFh) not code protected
0 = Block 3 (003000h-003FFFh) code protected
Code Protection bit
1 = Block 2 (002000h-002FFFh) not code protected
0 = Block 2 (002000h-002FFFh) code protected
Code Protection bit
1 = Block 1 (001000h-001FFFh) not code protected
0 = Block 1 (001000h-001FFFh) code protected
Code Protection bit
1 = Block 0 (000200h-000FFFh) not code protected
0 = Block 0 (000200h-000FFFh) code protected
MCLR Pin Enable bit
TMR0/GPCKI External Clock Mux bit
FLTA Mux bit
Stack Overflow Reset Enable bit
respectively. SDO output is multiplexed with RC7.
respectively. SDO output is multiplexed with RD1.
communication function)
Description
 2010 Microchip Technology Inc.