ATMEGA128L-8AJ Atmel, ATMEGA128L-8AJ Datasheet - Page 246
![IC MCU AVR 128K 8MHZ LV 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA128L-8AJ
Manufacturer Part Number
ATMEGA128L-8AJ
Description
IC MCU AVR 128K 8MHZ LV 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128L-8AJ
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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JTAG Interface
and On-chip
Debug System
Features
Overview
Test Access Port –
TAP
246
ATmega128
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The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
•
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A brief description is given in the following sections. Detailed descriptions for Programming via
the JTAG interface, and using the Boundary-scan Chain can be found in the sections
ming Via the JTAG Interface” on page 305
252, respectively. The On-chip Debug support is considered being private JTAG instructions,
and distributed within ATMEL and to selected third party vendors only.
Figure 120
TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller
selects either the JTAG Instruction Register or one of several Data Registers as the scan chain
(Shift Register) between the TDI – input and TDO – output. The Instruction Register holds JTAG
instructions controlling the behavior of a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the data registers used for
board-level testing. The JTAG Programming Interface (actually consisting of several physical
and virtual Data Registers) is used for serial programming via the JTAG interface. The Internal
Scan Chain and Break Point Scan Chain are used for On-chip debugging only.
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins
constitute the Test Access Port –– TAP. These pins are:
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JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
Debugger Access to:
Extensive On-chip Debug Support for Break Conditions, Including
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
On-chip Debugging Supported by AVR Studio
– All Internal Peripheral Units
– Internal and External RAM
– The Internal Register File
– Program Counter
– EEPROM and Flash Memories
– AVR Break Instruction
– Break on Change of Program Memory Flow
– Single Step Break
– Program Memory Breakpoints on Single Address or Address Range
– Data Memory Breakpoints on Single Address or Address Range
Testing PCBs by using the JTAG Boundary-scan capability
Programming the non-volatile memories, Fuses and Lock bits
On-chip debugging
TMS: Test mode select. This pin is used for navigating through the TAP-controller state
machine.
TCK: Test clock. JTAG operation is synchronous to TCK.
TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data
Register (Scan Chains).
TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
shows a block diagram of the JTAG interface and the On-chip Debug system. The
and
“IEEE 1149.1 (JTAG) Boundary-scan” on page
2467V–AVR–02/11
“Program-
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