ATMEGA64-16AJ Atmel, ATMEGA64-16AJ Datasheet - Page 170
ATMEGA64-16AJ
Manufacturer Part Number
ATMEGA64-16AJ
Description
IC MCU AVR 64K 5V 16MHZ 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64-16AJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Data Modes
2490Q–AVR–06/10
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
77
ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing
70
Table 73. CPOL and CPHA Functionality
Figure 77. SPI Transfer Format with CPHA = 0
Figure 78. SPI Transfer Format with CPHA = 1
and
and
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
Table
Figure
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB first (DORD = 0)
LSB first (DORD = 1)
71, as done below:
78. Data bits are shifted out and latched in on opposite edges of the SCK signal,
MSB
LSB
MSB
LSB
Sample (Falling)
Sample (Rising)
Leading Edge
Setup (Rising)
Setup (Falling)
Bit 6
Bit 1
Bit 6
Bit 1
Bit 5
Bit 2
Bit 5
Bit 2
Bit 4
Bit 3
Sample (Falling)
Sample (Rising)
Bit 4
Bit 3
Setup (Falling)
Trailing Edge
Setup (Rising)
Bit 3
Bit 4
Bit 3
Bit 4
Bit 2
Bit 5
Bit 2
Bit 5
ATmega64(L)
Bit 1
Bit 6
SPI Mode
Bit 1
Bit 6
0
1
2
3
LSB
MSB
LSB
MSB
Figure
Table
170
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