ATMEGA64L-8MJ Atmel, ATMEGA64L-8MJ Datasheet - Page 109
ATMEGA64L-8MJ
Manufacturer Part Number
ATMEGA64L-8MJ
Description
IC MCU AVR 64K 5V 8MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64L-8MJ
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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TIMSK –
Timer/Counter
Interrupt Mask
Register
TIFR – Timer/Counter
Interrupt Flag Register
2490Q–AVR–06/10
•
• Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable
When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter0 occurs, that is, when the OCF0 bit is set in the Timer/Coun-
ter Interrupt Flag Register – TIFR.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter Inter-
rupt Flag Register – TIFR.
• Bit 1 – OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when a Compare Match occurs between the Timer/Counter0 and the
data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare Match Interrupt Enable), and
OCF0 are set (one), the Timer/Counter0 Compare Match Interrupt is executed.
Bit
0x37 (0x57)
Read/Write
Initial Value
Bit
0x36 (0x56)
Read/Write
Initial Value
1. Write any value to either of the registers OCR0 or TCCR0.
2. Wait for the corresponding Update Busy Flag to be cleared.
3. Read TCNT0.
During asynchronous operation, the synchronization of the interrupt flags for the
asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting
of the interrupt flag. The Output Compare pin is changed on the timer clock and is not
synchronized to the processor clock.
OCF2
R/W
7
0
OCIE2
R/W
7
0
TOV2
R/W
6
0
TOIE2
R/W
6
0
ICF1
R/W
TICIE1
5
0
R/W
5
0
OCF1A
R/W
OCIE1A
4
0
R/W
4
0
OCF1B
OCIE1B
R/W
R/W
3
0
3
0
TOV1
R/W
TOIE1
R/W
2
0
2
0
OCF0
OCIE0
R/W
R/W
1
0
1
0
ATmega64(L)
TOV0
TOIE0
R/W
R/W
0
0
0
0
TIMSK
TIFR
109
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