AT80C51RD2-SLSIM Atmel, AT80C51RD2-SLSIM Datasheet - Page 11

• Manufacturer Part Number: AT80C51RD2-SLSIM
• Description: IC MCU 8051 5V SPI 20MHZ 44-PLCC
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51RD2-SLSIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4113D–8051–01/09
Reset Value = 0000 000’HCB.X2’b (see Hardware Config Byte)
Not bit addressable
Number
Bit
5
4
3
2
1
0
Mnemonic
PCAX2
T2X2
T1X2
T0X2
SIX2
Bit
X2
Description
Programmable Counter Array clock (This control bit is validated when the CPU
clock X2 is set; when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU
clock X2 is set; when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer 2 clock (This control bit is validated when the CPU clock X2 is set; when X2 is
low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer 1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is
low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
Timer 0 clock (This control bit is validated when the CPU clock X2 is set; when X2 is
low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
CPU clock
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and all the
peripherals.
Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual
peripherals "X2" bits.
Programmed by hardware after Power-up regarding Hardware Config Byte (HCB).
AT80C51RD2
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