AT80C51RD2-SLSIM Atmel, AT80C51RD2-SLSIM Datasheet - Page 24

• Manufacturer Part Number: AT80C51RD2-SLSIM
• Description: IC MCU 8051 5V SPI 20MHZ 44-PLCC
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51RD2-SLSIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

24
AT80C51RD2
Table 10-1.
CMOD - PCA Counter Mode Register (D9h)
Reset Value = 00XX X000b
Not bit addressable
The CMOD register includes three additional bits associated with the PCA (see Figure 10-4 and
Table 10-1).
The CCON register contains the run control bit for the PCA and the flags for the PCA timer (CF)
and each module (see Table 10-2).
• The CIDL bit which allows the PCA to stop during idle mode.
• The WDTE bit which enables or disables the watchdog function on module 4.
• The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON
• Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this
• Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be
Number
SFR) to be set when the PCA timer overflows.
bit.
generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by
software.
CIDL
Bit
7
7
6
5
4
3
2
1
0
Mnemonic
CMOD Register
WDTE
WDTE
CPS1
CPS0
CIDL
ECF
Bit
6
-
-
-
Description
Counter Idle Control
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
Watchdog Timer Enable
Cleared to disable Watchdog Timer function on PCA Module 4.
Set to enable Watchdog Timer function on PCA Module 4.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA Count Pulse Select
CPS1CPS0
0
0
1
1
PCA Enable Counter Overflow Interrupt
Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
0 Timer 0 Overflow
5
-
0
1
1
Selected PCA input
Internal clock f
Internal clock f
External clock at ECI/P1.2 pin (max rate = f
4
-
CLK PERIPH/6
CLK PERIPH/2
3
-
CPS1
2
CLK PERIPH/4
CPS0
1
)
4113D–8051–01/09
ECF
0