AT80C51RD2-RLTIM Atmel, AT80C51RD2-RLTIM Datasheet - Page 39

• Manufacturer Part Number: AT80C51RD2-RLTIM
• Description: IC MCU 8051 5V SPI 20MHZ 44-VQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51RD2-RLTIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4113D–8051–01/09
Table 11-4.
SCON - Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
FE/SM0
Number
Bit
7
7
6
5
4
3
2
1
0
Mnemonic
SCON Register
SM1
SM0
SM1
SM2
REN
TB8
RB8
Bit
FE
6
RI
TI
Description
Framing Error bit (SMOD0 = 1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
Serial port Mode bit 1
SM1ModeDescriptionBaud Rate
0
1
0
1
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually
mode 1. This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3
o transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2=0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop
bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 11-2. and Figure
11-3. in the other modes.
SM2
0Shift Registerf
18-bit UARTVariable
29-bit UARTf
39-bit UARTVariable
5
CPU PERIPH /32 or /16
REN
CPU PERIPH/6
4
TB8
3
RB8
2
AT80C51RD2
TI
1
RI
0
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