AT91SAM7A2-AU Atmel, AT91SAM7A2-AU Datasheet - Page 10

• Manufacturer Part Number: AT91SAM7A2-AU
• Description: IC ARM7 MCU 32BIT ROMLESS176LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A2-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 30MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

ADC: Analog to
Digital Converter
PMC: Power
Management
Controller
ICE Debug Mode
10
AT91SAM7A2 - Summary
PRELIMINARY
The two identical 8-channel 10-bit Analog-to-Digital Converters (ADC) are based on a Succes-
sive Approximation Register (SAR) approach. Each ADC has 8 analog input pins, ANA0IN0 to
ANA0IN7 and ANA1IN0 to ANA1IN7, and provides an interrupt signal to the AIC. Both ADCs
share the analog power supply pins V
V
The ADC can be configured to automatically enter Sleep Mode after a conversion sequence,
and can be triggered by the software. The ADC allows a data transfer with the PDC.
The AT91SAM7A2 Power Management Controller allows optimization of power consumption.
The PMC enables/disables the clock inputs of the PDC and ARM core. Moreover, the main
oscillator, the PLL and the analog peripherals can be put in standby mode allowing minimum
power consumption to be obtained. The PMC provides the following operating modes:
•
•
•
Each peripheral clock can be independently stopped or started directly in the peripheral to fur-
ther reduce power consumption in Normal, Wait and Slow Modes.
ARM Standard Embedded In Circuit Emulation is supported via the ICE port. It is connected to
a host computer via an external ICE Interface. In ICE Debug Mode the ARM core responds
with a non-JTAG chip ID which identifies the core to the ICE system. This is not JTAG IEEE
1149.1 compliant.
REFP
Normal: the clock generator provides clock to chip.
Wait Mode: the ARM core clock is deactivated.
Slow Mode: the clock generator is deactivated, the system is clocked at 32.768 kHz.
. Each channel can be enabled or disabled independently, and has its own data register.
DDA
and GNDA, and the input reference voltage pin
6021BS–ATARM–06-Jul-04