PIC16F716-I/ML Microchip Technology, PIC16F716-I/ML Datasheet - Page 55

• Manufacturer Part Number: PIC16F716-I/ML
• Description: IC PIC MCU FLASH 2KX14 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F716-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

8.3.1
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 8-1.
EQUATION 8-1:
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set. (Exception: If the PWM duty
• The PWM duty cycle is latched from CCPR1L into
© 2007 Microchip Technology Inc.
cycle = 0%, the pin will not be set.)
CCPR1H.
Note:
PWM Period
PWM PERIOD
The Timer2 postscaler (see Section 6.0
“Timer2 Module”) is not used in the
determination of the PWM frequency.
=
(TMR2 Prescale Value)
[
PWM PERIOD
(
PR2
)
+
1
] 4 T
•
•
OSC
•
8.3.2
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPR1L register and
DC1B<1:0> bits of the CCP1CON register. The
CCPR1L contains the eight MSbs and the DC1B<1:0>
bits of the CCP1CON register contain the two LSbs.
CCPR1L and DC1B<1:0> bits of the CCP1CON
register can be written to at any time. The duty cycle
value is not latched into CCPR1H until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPR1H
register is read-only.
Equation 8-2 is used to calculate the PWM pulse width.
Equation 8-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 8-2:
EQUATION 8-3:
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (F
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPR1H and 2-
bit latch, then the CCP1 pin is cleared (see Figure 8-3).
Duty Cycle Ratio
Pulse Width
PWM DUTY CYCLE
=
(
T
=
CCPR1L:CCP1CON<5:4>
OSC
PULSE WIDTH
DUTY CYCLE RATIO
(
---------------------------------------------------------------------- -
CCPR1L:CCP1CON<5:4>
PIC16F716
•
(TMR2 Prescale Value)
4 PR2
(
DS41206B-page 53
+
OSC
1
)
), or 2 bits of
)
•
)