PIC16F716-I/ML Microchip Technology, PIC16F716-I/ML Datasheet - Page 70
![IC PIC MCU FLASH 2KX14 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F716-I/ML
Manufacturer Part Number
PIC16F716-I/ML
Description
IC PIC MCU FLASH 2KX14 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F716-ISO.pdf
(136 pages)
4.PIC16F716-ISO.pdf
(12 pages)
Specifications of PIC16F716-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F716-ISO PDF datasheet #3
- PIC16F716-ISO PDF datasheet #4
- Current page: 70 of 136
- Download datasheet (3Mb)
PIC16F716
9.8
On power-up, the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 9-10,
Figure 9-11,
sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-12). This is useful for testing purposes or to
synchronize more than one PIC16F716 device
operating in parallel.
Table 9-5 shows the Reset conditions for some Special
Function Registers, while Table 9-6 shows the Reset
conditions for all the registers.
TABLE 9-3:
TABLE 9-4:
DS41206B-page 68
XT, HS, LP
RC
POR
0
0
0
0
1
1
1
1
1
Oscillator Configuration
Time-out Sequence
BOR
x
1
x
x
0
1
1
1
1
and
TIME-OUT IN VARIOUS SITUATIONS
STATUS BITS AND THEIR SIGNIFICANCE
TO
1
1
0
x
1
0
0
u
1
Figure 9-12
PD
1
1
x
0
1
1
0
u
0
Power-on Reset (BOREN = 0)
Power-on Reset (BOREN = 1)
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during Sleep or interrupt wake-up from Sleep
depict
72 ms + 1024 T
PWRTE = 0
time-out
72 ms
Power-up or Brown-out
OSC
9.9
The Power Control/STATUS Register, PCON has two
bits.
Bit 0 is the Brown-out Reset Status bit, BOR. If the
BOREN Configuration bit is set, BOR is ‘1’ on
Power-on Reset and reset to ‘0’ when a Brown-out con-
dition occurs. BOR must then be set by the user and
checked on subsequent resets to see if it is clear, indi-
cating that another Brown-out has occurred.
If the BOREN Configuration bit is clear, BOR is
unknown on Power-on Reset.
Bit 1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
PWRTE = 1
1024 T
Power Control/STATUS Register
(PCON)
—
OSC
© 2007 Microchip Technology Inc.
Wake-up from Sleep
1024 T
—
OSC
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