AT80C51SND1C-ROTUL Atmel, AT80C51SND1C-ROTUL Datasheet - Page 125

• Manufacturer Part Number: AT80C51SND1C-ROTUL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

16.8.0.1
4109L–8051–02/08
Reset Value = 0000 0000b
Table 114. MMCON1 Register
MMCON1 (S:E5h) – MMC Control Register 1
Reset Value = 0000 0000b
Number
Number
BLEN3
7 - 4
Bit
Bit
6
5
4
3
2
1
0
7
3
2
1
0
Mnemonic Description
Mnemonic Description
MBLOCK
RESPEN
BLEN3:0
CRCDIS
DATDIR
CMDEN
DTPTR
CRPTR
CTPTR
DATEN
BLEN2
DFMT
RFMT
Bit
Bit
6
Data Transmit Pointer Reset Bit
Set to reset the write pointer of the data FIFO.
Clear to release the write pointer of the data FIFO.
Command Receive Pointer Reset Bit
Set to reset the read pointer of the receive command FIFO.
Clear to release the read pointer of the receive command FIFO.
Command Transmit Pointer Reset Bit
Set to reset the write pointer of the transmit command FIFO.
Clear to release the read pointer of the transmit command FIFO.
Multi-block Enable Bit
Set to select multi-block data format.
Clear to select single block data format.
Data Format Bit
Set to select the block-oriented data format.
Clear to select the stream data format.
Response Format Bit
Set to select the 48-bit response format.
Clear to select the 136-bit response format.
Clear to enable the CRC7 computation when receiving a response.
Block Length Bits
Refer to Table 112 for bits description. Do not program value > 1011b
Data Direction Bit
Set to select data transfer from host to card (write mode).
Clear to select data transfer from card to host (read mode).
Data Transmission Enable Bit
Set and clear to enable data transmission immediately or after response has
been received.
Response Enable Bit
Set and clear to enable the reception of a response following a command
transmission.
CRC7 Disable Bit
Set to disable the CRC7 computation when receiving a response.
Command Transmission Enable Bit
Set and clear to enable transmission of the command FIFO to the card.
BLEN1
5
BLEN0
4
DATDIR
3
AT8xC51SND1C
DATEN
2
RESPEN
1
CMDEN
0
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