AT80C51SND1C-ROTUL Atmel, AT80C51SND1C-ROTUL Datasheet - Page 16
AT80C51SND1C-ROTUL
Manufacturer Part Number
AT80C51SND1C-ROTUL
Description
IC MCU FLASH MP3 DECODER 80-TQFP
Manufacturer
Atmel
Series
80Cr
Datasheet
1.AT80C51SND1C-ROTIL.pdf
(213 pages)
Specifications of AT80C51SND1C-ROTUL
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
Peripherals
Audio, I²S, MP3, PCM, POR, WDT
Number Of I /o
44
Program Memory Type
ROMless
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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5.4
16
Registers
AT8xC51SND1C
Table 16. CKCON Register
CKCON (S:8Fh) – Clock Control Register
Reset Value = 0000 000Xb (AT89C51SND1C) or 0000 0000b (AT83SND1C)
Table 17. PLLCON Register
PLLCON (S:E9h) – PLL Control Register
Number
Number
TWIX2
7 - 6
5 - 4
Bit
R1
Bit
7
7
6
5
4
3
2
1
0
7
3
Mnemonic Description
Mnemonic Description
PLLRES
TWIX2
WDX2
WDX2
T1X2
T0X2
SIX2
R1:0
Bit
X2
R0
Bit
6
6
-
-
-
Two-Wire Clock Control Bit
Set to select the oscillator clock divided by 2 as TWI clock input (X2
independent).
Clear to select the peripheral clock as TWI clock input (X2 dependent).
Watchdog Clock Control Bit
Set to select the oscillator clock divided by 2 as watchdog clock input (X2
independent).
Clear to select the peripheral clock as watchdog clock input (X2 dependent).
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Enhanced UART Clock (Mode 0 and 2) Control Bit
Set to select the oscillator clock divided by 2 as UART clock input (X2
independent).
Clear to select the peripheral clock as UART clock input (X2 dependent)..
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Timer 1 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 1 clock input (X2
independent).
Clear to select the peripheral clock as timer 1 clock input (X2 dependent).
Timer 0 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 0 clock input (X2
independent).
Clear to select the peripheral clock as timer 0 clock input (X2 dependent).
System Clock Control Bit
Clear to select 12 clock periods per machine cycle (STD mode, F
F
Set to select 6 clock periods per machine cycle (X2 mode, F
PLL Least Significant Bits R Divider
2 LSB of the 10-bit R divider.
Reserved
The values read from these bits are always 0. Do not set these bits.
PLL Reset Bit
Set this bit to reset the PLL.
Clear this bit to free the PLL and allow enabling.
OSC
/
5
5
-
2).
-
SIX2
4
4
-
PLLRES
3
3
-
T1X2
2
2
-
PLLEN
T0X2
1
CPU
1
4109L–8051–02/08
= F
CPU
PER
= F
PLOCK
= F
X2
PER
0
0
OSC
=
).
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